50 lines
931 B
Systemverilog
50 lines
931 B
Systemverilog
/////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2013-2018 Efinix Inc. All rights reserved.
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//
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// Single Port ROM
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//
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// *******************************
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// Revisions:
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// 0.0 Initial rev
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// 1.0 Finalized RTL macro
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// *******************************
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module rom
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#(
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parameter DATA_WIDTH = 16,
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parameter ADDR_WIDTH = 8,
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parameter OUTPUT_REG = "FALSE",
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parameter RAM_INIT_FILE = "init_hex.mem"
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)
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(
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input [ADDR_WIDTH-1:0] addr,
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input clk,
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output [DATA_WIDTH-1:0] data
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);
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localparam MEMORY_DEPTH = 2**ADDR_WIDTH;
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reg [DATA_WIDTH-1:0]r_rdata_1P;
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reg [DATA_WIDTH-1:0]r_rdata_2P;
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reg [DATA_WIDTH-1:0] rom[MEMORY_DEPTH-1:0];
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initial begin
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$readmemh(RAM_INIT_FILE, rom);
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end
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always@(posedge clk)
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begin
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r_rdata_1P <= rom[addr];
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r_rdata_2P <= r_rdata_1P;
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end
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generate
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if (OUTPUT_REG == "TRUE")
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assign data = r_rdata_2P;
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else
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assign data = r_rdata_1P;
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endgenerate
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endmodule
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