30 lines
554 B
Systemverilog
30 lines
554 B
Systemverilog
module interrupt_controller
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(
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input clk,
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input reset,
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input [7:0] i_data,
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output logic [7:0] o_data,
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input cs,
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input rwb,
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output logic irqb_master,
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input irqb0, irqb1, irqb2, irqb3,
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input irqb4, irqb5, irqb6, irqb7
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);
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//All of the inputs are low level triggered.
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logic [7:0] irqbv;
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assign irqbv = {irqb0, irqb1, irqb2, irqb3, irqb4, irqb5, irqb6, irqb7};
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always @(posedge clk) begin
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o_data <= irqbv;
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irqb_master = &irqbv;
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if (cs & ~rwb) begin
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o_data <= o_data | i_data;
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end
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end
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endmodule |