2f79a00000
address decoding is now performed on the translated address which comes from the memory mapper, instead of the address coming directly from the cpu. This means that you can access the full amount of ram at any address that it is mapped to.
73 lines
1.9 KiB
Systemverilog
73 lines
1.9 KiB
Systemverilog
module testbench();
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timeunit 10ns;
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timeprecision 1ns;
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logic [23:0] addr;
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logic sdram_cs;
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logic rom_cs;
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logic hex_cs;
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logic board_io_cs;
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logic uart_cs;
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logic irq_cs;
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logic mm_cs2;
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logic mm_cs1;
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int cs_count = sdram_cs + rom_cs + hex_cs + uart_cs + board_io_cs + mm_cs2 + mm_cs1;
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addr_decode dut(.*);
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initial begin : TEST_VECTORS
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for (int i = 0; i < 2**24; i++) begin
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addr <= i;
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#1
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assert(cs_count < 2)
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else
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$error("Multiple chip selects present!");
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if (i < 16'h7fe0 || i >= 24'h010000) begin
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assert(sdram_cs == '1)
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else
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$error("Bad CS! addr=%4x should have sdram_cs!", addr);
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end
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if (i >= 16'h7ff0 && i < 16'h7ff4) begin
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assert(hex_cs == '1)
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else
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$error("Bad CS! addr=%4x should have hex_cs!", addr);
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end
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if (i >= 16'h7ff4 && i < 16'h7ff6) begin
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assert(uart_cs == '1)
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else
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$error("Bad CS! addr=%4x should have uart_cs!", addr);
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end
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if (i == 16'h7ff6) begin
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assert(board_io_cs == '1)
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else
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$error("Bad CS! addr=%4x should have board_io_cs!", addr);
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end
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if (i == 16'h7ff7) begin
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assert(mm_cs2 == '1)
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else
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$error("Bad CS! addr=%4x should have mm_cs2!", addr);
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end
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if (i >= 16'h7fe0 && i < 16'h7ff0) begin
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assert(mm_cs1 == '1)
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else
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$error("Bad CS! addr=%4x should have mm_cs1!", addr);
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end
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if (i == 16'h7fff) begin
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assert(irq_cs == '1)
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else
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$error("Bad CS! addr=%4x should have irq_cs!", addr);
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end
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if (i >= 2**15 && i < 24'h010000) begin
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assert(rom_cs == '1)
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else
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$error("Bad CS! addr=%4x should have rom_cs!", addr);
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end
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end
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end
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endmodule
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