132 lines
2.6 KiB
Systemverilog
132 lines
2.6 KiB
Systemverilog
module timer
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(
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input clk,
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input reset,
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input [7:0] i_data,
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output logic [7:0] o_data,
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input cs,
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input rwb,
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input [1:0] addr,
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output logic irqb
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);
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//new idea for timer:
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//it can either be oneshot or repeating
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//it can either cause an interrupt or not.
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//if you want it to do both, add another timer.
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/*
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Addr Read Write
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0 Counter Low Latch Low
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1 Counter High Latch High
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2 Divisor Divisor
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3 Status Control
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*/
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logic [15:0] timer_latch, timer_counter;
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//control register
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// bit 0: Enable interrupts
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// bit 1: Enable 1 shot mode
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//writing to latch low starts the timer
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logic [7:0] divisor, status, control;
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logic count_en;
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assign status[0] = count_en;
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logic [15:0] pulsecount;
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//I think this should be negedge so that writes go through
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always @(negedge clk) begin
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if (reset) begin
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count_en = '0;
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timer_counter <= '0;
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pulsecount <= '0;
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timer_latch <= '1;
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divisor <= '0;
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control <= '0;
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irqb <= '1;
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end else begin
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if (count_en) begin
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if (pulsecount[15:8] == divisor) begin
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timer_counter <= timer_counter + 16'b1;
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pulsecount <= '0;
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end else begin
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pulsecount <= pulsecount + 16'b1;
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end
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end
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if (timer_counter == timer_latch) begin
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// if interrupts are enabled
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if (control[0]) begin
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irqb <= '0;
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end
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// if oneshot mode is enabled
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if (control[1]) begin
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count_en <= '0;
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end else begin
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timer_counter <= '0;
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end
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end
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if (cs & rwb) begin
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irqb <= '1;
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end
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if (cs & ~rwb) begin
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case (addr)
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2'h0: begin
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count_en <= '1;
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timer_latch[7:0] <= i_data;
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end
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2'h1: begin
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timer_latch[15:8] <= i_data;
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end
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2'h2: begin
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divisor <= i_data;
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end
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2'h3: begin
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control <= i_data;
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end
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endcase
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end
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end
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end
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always_comb begin
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o_data = '0;
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unique case (addr)
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2'h0: begin
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o_data = timer_counter[7:0];
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end
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2'h1: begin
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o_data = timer_counter[15:8];
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end
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2'h2: begin
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o_data = divisor;
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end
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2'h3: begin
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o_data = status;
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end
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endcase
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end
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endmodule
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