150 lines
3.5 KiB
Systemverilog
150 lines
3.5 KiB
Systemverilog
module timer
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(
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input clk,
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input reset,
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input [7:0] i_data,
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output logic [7:0] o_data,
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input cs,
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input rwb,
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input [2:0] addr,
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output logic irq
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);
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logic [16:0] tick_counter_reg, irq_counter_reg;
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logic [7:0] divisor, status, control;
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// --------------------------------
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// | 0 | Tick Counter Low |
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// --------------------------------
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// | 1 | Tick Counter High |
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// --------------------------------
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// | 2 | IRQ Counter Low |
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// --------------------------------
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// | 3 | IRQ Counter High |
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// --------------------------------
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// | 4 | Reserved |
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// --------------------------------
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// | 5 | Divisor |
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// --------------------------------
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// | 6 | Status |
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// --------------------------------
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// | 7 | Control |
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// --------------------------------
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// Tick counter register
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// The tick counter register is read only. It starts at 0 upon
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// reset and increments continuously according to the divsor.
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// IRQ Counter Register
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// The IRQ counter register is writable, which is how you set the desired
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// time to count down. Writing to the high register does nothing, while
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// writing to the low register will begin the countdown. Based on the control
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// register, the register will reset itself when it reaches 0 and triggers an
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// interrupt. See the control register for more details.
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// Divisor
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// The divisor register controls how fast the timer counts up. The divisor is
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// bit shifted left by 8 (multiplied by 256), and that is the number of pulses
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// it takes to increment the counters.
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// Status
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// 6:0 Reserved
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// 7: Interrupt. Set if an interrupt has occured. Write to clear.
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// Control
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// 0: Oneshot. Set if you only want the timer to run once.
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// 7:1 Reserved
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// What features do we want for the timer?
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// 1. Tracking elapsed time
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// 2. Trigger interrupts (repeated or elapsed)
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// General Idea
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// Takes in the input clock and can set a divisor
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// of a power of 2. Every time that many clock pulses
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// occur, it will increment the counter. The counter
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// can then be read at any point.
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// The interrupts will have a difference counter which
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// counts down. When the counter reaches 0, it will trigger
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// an interrupt and optionally reset the counter to start
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// again.
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logic [15:0] pulsecount;
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logic [15:0] tickcount;
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//I think this should be negedge so that writes go through
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always @(negedge clk) begin
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if (reset) begin
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tickcount <= '0;
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pulsecount <= '0;
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tick_counter_reg <= '0;
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irq_counter_reg <= '0;
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divisor <= '0;
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status <= '0;
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control <= '0;
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end else begin
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if (pulsecount[15:8] == divisor) begin
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tickcount <= tickcount + 16'b1;
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pulsecount <= '0;
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end else begin
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pulsecount <= pulsecount + 16'b1;
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end
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if (cs & ~rwb) begin
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case (addr)
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3'h5: begin
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divisor <= i_data;
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end
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endcase
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end
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end
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end
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always_comb begin
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o_data = '0;
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unique case (addr)
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3'h0: begin
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o_data = tickcount[7:0];
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end
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3'h1: begin
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o_data = tickcount[15:8];
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end
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3'h2: begin
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end
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3'h3: begin
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end
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3'h4: begin
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end
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3'h5: begin
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end
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3'h6: begin
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end
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3'h7: begin
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end
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endcase
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end
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endmodule
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