44 lines
777 B
Systemverilog
44 lines
777 B
Systemverilog
module sim_uart(
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input clk,
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input clk_50,
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input reset,
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input [7:0] i_data,
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input rx_i,
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output tx_o
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);
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logic tx_busy, rx_busy;
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logic rx_data_valid, rx_error, rx_parity_error;
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logic baud_x16_ce;
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logic tx_en;
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logic [7:0] tx_data, rx_data;
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uart u_uart(
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.tx_o ( tx_o ),
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.rx_i ( rx_i ),
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.tx_busy ( tx_busy ),
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.rx_data ( rx_data ),
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.rx_data_valid ( rx_data_valid ),
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.rx_error ( rx_error ),
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.rx_parity_error ( rx_parity_error ),
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.rx_busy ( rx_busy ),
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.baud_x16_ce ( baud_x16_ce ),
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.clk ( clk_50 ),
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.reset ( reset ),
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.tx_data ( tx_data ),
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.baud_rate ( baud_rate ),
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.tx_en ( tx_en )
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);
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always @(posedge baud_x16_ce) begin
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if (rx_data_valid)
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$display("UART: %c", rx_data);
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end
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endmodule
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