113 lines
2.1 KiB
Systemverilog
113 lines
2.1 KiB
Systemverilog
`timescale 1ns/1ps
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module mapper_tb();
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logic r_clk_cpu;
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// clk_cpu
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initial begin
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r_clk_cpu <= '1;
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forever begin
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#125 r_clk_cpu <= ~r_clk_cpu;
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end
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end
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logic reset;
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logic [15:0] addr;
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logic [24:0] map_addr;
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logic [7:0] i_data;
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logic [7:0] o_data;
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logic cs;
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logic rwb;
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mapper u_mapper(
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.i_reset(reset),
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.i_clk(r_clk_cpu),
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.i_cs(cs),
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.i_we(~rwb),
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.i_data(i_data),
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.o_data(o_data),
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.i_cpu_addr(addr),
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.o_mapped_addr(map_addr)
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);
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/* These could be made better probably */
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task write_reg(input logic [4:0] _addr, input logic [7:0] _data);
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@(negedge r_clk_cpu);
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cs <= '1;
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addr <= _addr;
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rwb <= '0;
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i_data <= '1;
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@(posedge r_clk_cpu);
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i_data <= _data;
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@(negedge r_clk_cpu);
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cs <= '0;
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rwb <= '1;
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endtask
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task read_reg(input logic [2:0] _addr, output logic [7:0] _data);
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@(negedge r_clk_cpu);
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cs <= '1;
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addr <= _addr;
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rwb <= '1;
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i_data <= '1;
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@(posedge r_clk_cpu);
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_data <= o_data;
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@(negedge r_clk_cpu);
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cs <= '0;
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rwb <= '1;
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endtask
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int errors;
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int rnd_values [16];
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initial begin
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for (int i = 0; i < 16; i++) begin
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rnd_values[i] = $urandom();
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end
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errors = 0;
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repeat (5) @(posedge r_clk_cpu);
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reset = 1;
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cs = 0;
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rwb = 1;
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addr = '0;
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i_data = '0;
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repeat (5) @(posedge r_clk_cpu);
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reset = 0;
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repeat (5) @(posedge r_clk_cpu);
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for (int i = 0; i < 16; i++) begin
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write_reg(2*i, rnd_values[i][7:0]);
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write_reg(2*i + 1, rnd_values[i][15:8]);
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end
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repeat (5) @(posedge r_clk_cpu);
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for (int i = 0; i < 16; i++) begin
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assert (u_mapper.mm[i] == rnd_values[i][15:0]) else begin
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$error("mm[%d] expected 0x%x got 0x%x", i, rnd_values[i][15:0], u_mapper.mm[i]);
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errors += 1;
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end
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end
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if (errors != 0) begin
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$finish_and_return(-1);
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end else begin
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$finish();
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end
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end
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initial
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begin
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$dumpfile("mapper_tb.vcd");
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$dumpvars(0,mapper_tb);
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for (int i = 0; i < 16; i++) $dumpvars(0, u_mapper.mm[i]);
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end
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endmodule
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