Files
super6502/hw/efinix_fpga/addr_decode.sv
Byron Lathi fcae23785e Throw everything up
I think that previously, I had not actually commited any of this to git.
This adds all of the new effinix stuff that I had been working on for
months.

The gist of all of this is that the intel fpga is expensive and does not
exist, whereas the effinix ones are not as expensive and more existant.
This redoes the project to use the dev board, as well as a custom board
that I may or may not make.
2022-10-04 17:15:49 -05:00

25 lines
753 B
Systemverilog

module addr_decode(
input logic [23:0] addr,
output logic sdram_cs,
output logic rom_cs,
output logic hex_cs,
output logic uart_cs,
output logic irq_cs,
output logic board_io_cs,
output logic mm_cs1,
output logic mm_cs2,
output logic sd_cs
);
assign rom_cs = addr >= 24'h008000 && addr < 24'h010000;
assign sdram_cs = addr < 24'h007fe0 || addr >= 24'h010000;
assign mm_cs1 = addr >= 24'h007fe0 && addr < 24'h007ff0;
assign hex_cs = addr >= 24'h007ff0 && addr < 24'h007ff4;
assign uart_cs = addr >= 24'h007ff4 && addr < 24'h007ff6;
assign board_io_cs = addr == 24'h007ff6;
assign mm_cs2 = addr == 24'h007ff7;
assign sd_cs = addr >= 24'h007ff8 && addr < 24'h007ffe;
assign irq_cs = addr == 24'h007fff;
endmodule