fcae23785e
I think that previously, I had not actually commited any of this to git. This adds all of the new effinix stuff that I had been working on for months. The gist of all of this is that the intel fpga is expensive and does not exist, whereas the effinix ones are not as expensive and more existant. This redoes the project to use the dev board, as well as a custom board that I may or may not make.
69 lines
2.0 KiB
Systemverilog
69 lines
2.0 KiB
Systemverilog
module sdram_adapter(
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input i_sysclk,
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input i_sdrclk,
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input i_tACclk,
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input i_pll_locked,
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output o_pll_reset,
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output o_sdr_CKE,
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output o_sdr_n_CS,
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output o_sdr_n_WE,
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output o_sdr_n_RAS,
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output o_sdr_n_CAS,
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output [1:0]o_sdr_BA,
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output [12:0]o_sdr_ADDR,
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input [15:0]i_sdr_DATA,
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output [15:0]o_sdr_DATA,
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output [15:0]o_sdr_DATA_oe,
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output [1:0]o_sdr_DQM
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);
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sdram u_sdram (
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.i_arst (w_areset),
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.i_sysclk (w_sysclk),
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.i_sdrclk (i_sdrclk),
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.i_tACclk (i_tACclk),
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.i_pll_locked (1'b1),
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.i_we (r_we_1P),
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.i_re (r_re_1P),
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.i_last (r_last_1P),
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.i_addr (r_addr_1P),
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.i_din (r_din_1P),
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.o_dout (w_dout),
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.o_sdr_state (w_sdr_state),
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.o_sdr_init_done (w_sdr_init_done),
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.o_wr_ack (w_wr_ack),
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.o_rd_ack (w_rd_ack),
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.o_ref_req (),
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.o_rd_valid (w_rd_valid),
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.o_sdr_CKE (w_sdr_CKE),
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.o_sdr_n_CS (w_sdr_n_CS),
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.o_sdr_n_RAS (w_sdr_n_RAS),
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.o_sdr_n_CAS (w_sdr_n_CAS),
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.o_sdr_n_WE (w_sdr_n_WE),
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.o_sdr_BA (w_sdr_BA),
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.o_sdr_ADDR (w_sdr_ADDR),
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.o_sdr_DATA (w_sdr_DATA),
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.o_sdr_DATA_oe (w_sdr_DATA_oe),
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.i_sdr_DATA ({{16{1'b0}}, i_sdr_DATA}),
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.o_sdr_DQM (w_sdr_DQM),
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.o_dbg_dly_cnt_b (w_dbg_dly_cnt_b),
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.o_dbg_tRCD_done (w_dbg_tRCD_done),
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.o_dbg_tRTW_done (w_dbg_tRTW_done),
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.o_dbg_ref_req (w_dbg_ref_req),
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.o_dbg_wr_ack (w_dbg_wr_ack),
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.o_dbg_rd_ack (w_dbg_rd_ack),
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.o_dbg_n_CS (w_dbg_n_CS),
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.o_dbg_n_RAS (w_dbg_n_RAS),
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.o_dbg_n_CAS (w_dbg_n_CAS),
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.o_dbg_n_WE (w_dbg_n_WE),
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.o_dbg_BA (w_dbg_BA),
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.o_dbg_ADDR (w_dbg_ADDR),
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.o_dbg_DATA_out (w_dbg_DATA_out),
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.o_dbg_DATA_in (w_dbg_DATA_in)
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);
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endmodule
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