fcae23785e
I think that previously, I had not actually commited any of this to git. This adds all of the new effinix stuff that I had been working on for months. The gist of all of this is that the intel fpga is expensive and does not exist, whereas the effinix ones are not as expensive and more existant. This redoes the project to use the dev board, as well as a custom board that I may or may not make.
32 lines
2.2 KiB
XML
32 lines
2.2 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2021.2.323.4.6" db_version="20212999" last_change_date="Thu Jun 9 21:34:24 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
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<efxpt:device_info>
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<efxpt:iobank_info>
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<efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
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<efxpt:iobank name="1B_1C" iostd="3.3 V LVTTL / LVCMOS"/>
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<efxpt:iobank name="1D_1E" iostd="3.3 V LVTTL / LVCMOS"/>
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<efxpt:iobank name="3A_3B_3C" iostd="3.3 V LVTTL / LVCMOS"/>
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<efxpt:iobank name="3D_3E" iostd="3.3 V LVTTL / LVCMOS"/>
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<efxpt:iobank name="4A" iostd="3.3 V LVTTL / LVCMOS"/>
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<efxpt:iobank name="4B" iostd="3.3 V LVTTL / LVCMOS"/>
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<efxpt:iobank name="BR" iostd="1.2 V"/>
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<efxpt:iobank name="TL" iostd="1.2 V"/>
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<efxpt:iobank name="TR" iostd="1.2 V"/>
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</efxpt:iobank_info>
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<efxpt:ctrl_info>
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<efxpt:ctrl name="cfg" ctrl_def="CONFIG_CTRL0" clock_name="" is_clk_invert="false" cbsel_bus_name="cfg_CBSEL" config_ctrl_name="cfg_CONFIG" ena_capture_name="cfg_ENA" error_status_name="cfg_ERROR" um_signal_status_name="cfg_USR_STATUS" is_remote_update_enable="false" is_user_mode_enable="false"/>
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</efxpt:ctrl_info>
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</efxpt:device_info>
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<efxpt:gpio_info device_def="T20F256">
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<efxpt:global_unused_config state="input with weak pullup"/>
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</efxpt:gpio_info>
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<efxpt:pll_info>
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<efxpt:pll name="pll_inst1" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.00" multiplier="32" pre_divider="1" post_divider="8" reset_name="" locked_name="" is_ipfrz="false" is_bypass_lock="true">
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<efxpt:output_clock name="pll_inst1_CLKOUT0" number="0" out_divider="200" adv_out_phase_shift="0"/>
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<efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="3" clksel_name="" feedback_clock_name="" feedback_mode="internal"/>
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</efxpt:pll>
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</efxpt:pll_info>
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<efxpt:lvds_info/>
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<efxpt:jtag_info/>
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</efxpt:design_db>
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