33 lines
506 B
Systemverilog
33 lines
506 B
Systemverilog
module SevenSeg(
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input clk,
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input rst,
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input rw,
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input [7:0] data,
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input cs,
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input addr,
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output logic [6:0] HEX0, HEX1, HEX2, HEX3
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);
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logic [7:0] _data [2];
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always_ff @(posedge clk) begin
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if (rst)
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_data = '{default:'0};
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if (~rw & cs)
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_data[addr] <= data;
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end
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logic [3:0] hex_4[3:0];
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assign {hex_4[3], hex_4[2]} = _data[1];
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assign {hex_4[1], hex_4[0]} = _data[0];
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HexDriver hex_drivers[3:0] (hex_4, {HEX3, HEX2, HEX1, HEX0});
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endmodule
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