Files
super6502/hw/efinix_fpga/addr_decode.sv
Byron Lathi 42ad901ba4 Add multiplier
Add 16x16 multiplier.

Pretty simple. Address 0-1 is multipled by address 2-3 and the result is
in address 4-7, all little endian of course.
2023-01-04 16:15:02 -05:00

18 lines
444 B
Systemverilog

module addr_decode
(
input [15:0] i_addr,
output o_rom_cs,
output o_leds_cs,
output o_timer_cs,
output o_multiplier_cs,
output o_sdram_cs
);
assign o_rom_cs = i_addr >= 16'hf000 && i_addr <= 16'hffff;
assign o_timer_cs = i_addr >= 16'heff8 && i_addr <= 16'heffb;
assign o_multiplier_cs = i_addr >= 16'heff0 && i_addr <= 16'heff7;
assign o_leds_cs = i_addr == 16'hefff;
assign o_sdram_cs = i_addr < 16'h8000;
endmodule