152 lines
2.8 KiB
Systemverilog
152 lines
2.8 KiB
Systemverilog
`timescale 1ns/1ps
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module sim_top();
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`include "include/super6502_sdram_controller_define.vh"
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logic r_sysclk, r_sdrclk, r_clk_50, r_clk_2;
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// clk_100
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initial begin
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r_sysclk <= '1;
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forever begin
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#5 r_sysclk <= ~r_sysclk;
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end
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end
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// clk_200
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initial begin
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r_sdrclk <= '1;
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forever begin
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#2.5 r_sdrclk <= ~r_sdrclk;
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end
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end
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// clk_50
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initial begin
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r_clk_50 <= '1;
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forever begin
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#10 r_clk_50 <= ~r_clk_50;
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end
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end
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// clk_2
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initial begin
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r_clk_2 <= '1;
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forever begin
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#250 r_clk_2 <= ~r_clk_2;
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end
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end
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initial begin
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$dumpfile("sim_top.vcd");
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$dumpvars(0,sim_top);
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end
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logic button_reset;
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initial begin
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button_reset <= '0;
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repeat(10) @(r_clk_2);
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button_reset <= '1;
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repeat(8000) @(r_clk_2);
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$finish();
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end
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logic w_cpu_reset;
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logic [15:0] w_cpu_addr;
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logic [7:0] w_cpu_data_from_cpu, w_cpu_data_from_dut;
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logic w_cpu_we;
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logic w_cpu_phi2;
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//TODO: this
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cpu_65c02 u_cpu(
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.phi2(w_cpu_phi2),
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.reset(~w_cpu_reset),
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.AB(w_cpu_addr),
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.RDY('1),
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.IRQ('0),
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.NMI('0),
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.DI_s1(w_cpu_data_from_dut),
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.DO(w_cpu_data_from_cpu),
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.WE(w_cpu_we)
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);
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// Having the super6502 causes an infinite loop,
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// but just the rom works. Need to whittle down
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// which block is causing it.
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// rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom(
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// .addr(w_cpu_addr[11:0]),
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// .clk(r_clk_2),
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// .data(w_cpu_data_from_dut)
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// );
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//TODO: also this
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super6502 u_dut(
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.i_sysclk(r_sysclk),
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.i_sdrclk(r_sdrclk),
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.i_tACclk(~r_sdrclk),
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.clk_50(r_clk_50),
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.clk_2(r_clk_2),
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.button_reset(button_reset),
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.cpu_resb(w_cpu_reset),
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.cpu_addr(w_cpu_addr),
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.cpu_data_out(w_cpu_data_from_dut),
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.cpu_data_in(w_cpu_data_from_cpu),
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.cpu_rwb(~w_cpu_we),
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.cpu_phi2(w_cpu_phi2),
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.o_sdr_CKE(w_sdr_CKE),
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.o_sdr_n_CS(w_sdr_n_CS),
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.o_sdr_n_WE(w_sdr_n_WE),
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.o_sdr_n_RAS(w_sdr_n_RAS),
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.o_sdr_n_CAS(w_sdr_n_CAS),
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.o_sdr_BA(w_sdr_BA),
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.o_sdr_ADDR(w_sdr_ADDR),
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.i_sdr_DATA(w_sdr_DQ),
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.o_sdr_DATA(w_sdr_DATA),
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.o_sdr_DATA_oe(w_sdr_DATA_oe),
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.o_sdr_DQM(w_sdr_DQM)
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);
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wire w_sdr_CKE;
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wire w_sdr_n_CS;
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wire w_sdr_n_WE;
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wire w_sdr_n_RAS;
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wire w_sdr_n_CAS;
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wire [BA_WIDTH -1:0]w_sdr_BA;
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wire [ROW_WIDTH -1:0]w_sdr_ADDR;
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wire [DQ_GROUP *DQ_WIDTH -1:0]w_sdr_DATA;
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wire [DQ_GROUP *DQ_WIDTH -1:0]w_sdr_DATA_oe;
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wire [DQ_GROUP -1:0]w_sdr_DQM;
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wire [DQ_GROUP *DQ_WIDTH -1:0]w_sdr_DQ;
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genvar i, j;
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generate
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for (i=0; i<DQ_GROUP*DQ_WIDTH; i=i+1)
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begin: DQ_map
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assign w_sdr_DQ[i] = (w_sdr_DATA_oe[i])?
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w_sdr_DATA[i]:1'bz;
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end
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for (j=0; j<DQ_GROUP; j=j+1)
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begin : mem_inst
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generic_sdr inst_sdr
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(
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.Dq(w_sdr_DQ[((j+1)*(DQ_WIDTH))-1:((j)*DQ_WIDTH)]),
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.Addr(w_sdr_ADDR[ROW_WIDTH-1:0]),
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.Ba(w_sdr_BA[BA_WIDTH-1:0]),
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.Clk(~r_sdrclk),
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.Cke(w_sdr_CKE),
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.Cs_n(w_sdr_n_CS),
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.Ras_n(w_sdr_n_RAS),
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.Cas_n(w_sdr_n_CAS),
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.We_n(w_sdr_n_WE),
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.Dqm(w_sdr_DQM[j])
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);
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end
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endgenerate
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endmodule |