467 lines
16 KiB
Systemverilog
467 lines
16 KiB
Systemverilog
module super6502_fpga(
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input logic i_sysclk, // Controller Clock (100MHz)
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input logic i_sdrclk, // t_su and t_wd clock (200MHz)
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input logic i_tACclk, // t_ac clock (200MHz)
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input clk_cpu,
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input button_reset,
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input pll_cpu_locked,
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output logic pll_cpu_reset,
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input i_pll_locked,
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output logic o_pll_reset,
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output logic o_sdr_CKE,
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output logic o_sdr_n_CS,
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output logic o_sdr_n_WE,
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output logic o_sdr_n_RAS,
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output logic o_sdr_n_CAS,
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output logic [1:0] o_sdr_BA,
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output logic [12:0] o_sdr_ADDR,
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input logic [15:0] i_sdr_DATA,
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output logic [15:0] o_sdr_DATA,
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output logic [15:0] o_sdr_DATA_oe,
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output logic [1:0] o_sdr_DQM,
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input [7:0] i_cpu0_data_from_cpu,
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input i_cpu0_sync,
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input i_cpu0_rwb,
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input logic [15:0] i_cpu0_addr,
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output logic [7:0] o_cpu0_data_from_dut,
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output logic [7:0] o_cpu0_data_oe,
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output logic o_cpu0_irqb,
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output logic o_cpu0_nmib,
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output logic o_cpu0_rdy,
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output logic o_cpu0_reset,
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output logic o_clk_phi2,
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input i_sd_cmd,
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output o_sd_cmd,
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output o_sd_cmd_oe,
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input i_sd_dat,
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output o_sd_dat,
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output o_sd_dat_oe,
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output o_sd_clk,
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output o_sd_cs
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);
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localparam ADDR_WIDTH = 32;
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localparam DATA_WIDTH = 32;
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assign pll_cpu_reset = '1;
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assign o_pll_reset = '1;
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assign o_cpu0_nmib = '1;
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assign o_clk_phi2 = clk_cpu;
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assign o_cpu0_data_oe = {8{i_cpu0_rwb}};
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logic vio0_reset;
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assign vio0_reset = '1;
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logic master_reset;
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logic sdram_ready;
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logic [3:0] w_sdr_state;
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logic pre_reset;
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assign pre_reset = button_reset & vio0_reset;
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assign sdram_ready = |w_sdr_state;
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assign master_reset = pre_reset & sdram_ready;
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assign o_sd_cs = '1;
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logic cpu0_AWVALID;
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logic cpu0_AWREADY;
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logic [ADDR_WIDTH-1:0] cpu0_AWADDR;
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logic cpu0_WVALID;
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logic cpu0_WREADY;
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logic [DATA_WIDTH-1:0] cpu0_WDATA;
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logic [DATA_WIDTH/8-1:0] cpu0_WSTRB;
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logic cpu0_BVALID;
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logic cpu0_BREADY;
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logic [1:0] cpu0_BRESP;
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logic cpu0_ARVALID;
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logic cpu0_ARREADY;
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logic [ADDR_WIDTH-1:0] cpu0_ARADDR;
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logic cpu0_RVALID;
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logic cpu0_RREADY;
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logic [DATA_WIDTH-1:0] cpu0_RDATA;
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logic [1:0] cpu0_RRESP;
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logic ram_awvalid;
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logic ram_awready;
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logic [ADDR_WIDTH-1:0] ram_awaddr;
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logic ram_wvalid;
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logic ram_wready;
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logic [DATA_WIDTH-1:0] ram_wdata;
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logic [DATA_WIDTH/8-1:0] ram_wstrb;
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logic ram_bvalid;
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logic ram_bready;
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logic [1:0] ram_bresp;
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logic ram_arvalid;
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logic ram_arready;
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logic [ADDR_WIDTH-1:0] ram_araddr;
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logic ram_rvalid;
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logic ram_rready;
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logic [DATA_WIDTH-1:0] ram_rdata;
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logic [1:0] ram_rresp;
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logic rom_awvalid;
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logic rom_awready;
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logic [ADDR_WIDTH-1:0] rom_awaddr;
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logic rom_wvalid;
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logic rom_wready;
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logic [DATA_WIDTH-1:0] rom_wdata;
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logic [DATA_WIDTH/8-1:0] rom_wstrb;
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logic rom_bvalid;
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logic rom_bready;
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logic [1:0] rom_bresp;
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logic rom_arvalid;
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logic rom_arready;
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logic [ADDR_WIDTH-1:0] rom_araddr;
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logic rom_rvalid;
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logic rom_rready;
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logic [DATA_WIDTH-1:0] rom_rdata;
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logic [1:0] rom_rresp;
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logic sdram_AWVALID;
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logic sdram_AWREADY;
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logic [ADDR_WIDTH-1:0] sdram_AWADDR;
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logic sdram_WVALID;
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logic sdram_WREADY;
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logic [DATA_WIDTH-1:0] sdram_WDATA;
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logic [DATA_WIDTH/8-1:0] sdram_WSTRB;
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logic sdram_BVALID;
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logic sdram_BREADY;
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logic [1:0] sdram_BRESP;
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logic sdram_ARVALID;
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logic sdram_ARREADY;
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logic [ADDR_WIDTH-1:0] sdram_ARADDR;
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logic sdram_RVALID;
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logic sdram_RREADY;
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logic [DATA_WIDTH-1:0] sdram_RDATA;
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logic [1:0] sdram_RRESP;
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// These are for the control/status registers
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logic sd_controller_csr_AWVALID;
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logic sd_controller_csr_AWREADY;
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logic [ADDR_WIDTH-1:0] sd_controller_csr_AWADDR;
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logic sd_controller_csr_WVALID;
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logic sd_controller_csr_WREADY;
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logic [DATA_WIDTH-1:0] sd_controller_csr_WDATA;
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logic [DATA_WIDTH/8-1:0] sd_controller_csr_WSTRB;
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logic sd_controller_csr_BVALID;
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logic sd_controller_csr_BREADY;
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logic [1:0] sd_controller_csr_BRESP;
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logic sd_controller_csr_ARVALID;
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logic sd_controller_csr_ARREADY;
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logic [ADDR_WIDTH-1:0] sd_controller_csr_ARADDR;
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logic sd_controller_csr_RVALID;
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logic sd_controller_csr_RREADY;
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logic [DATA_WIDTH-1:0] sd_controller_csr_RDATA;
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logic [1:0] sd_controller_csr_RRESP;
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// these are for the dma master.
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logic sd_controller_dma_AWVALID;
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logic sd_controller_dma_AWREADY;
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logic [ADDR_WIDTH-1:0] sd_controller_dma_AWADDR;
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logic sd_controller_dma_WVALID;
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logic sd_controller_dma_WREADY;
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logic [DATA_WIDTH-1:0] sd_controller_dma_WDATA;
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logic [DATA_WIDTH/8-1:0] sd_controller_dma_WSTRB;
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logic sd_controller_dma_BVALID;
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logic sd_controller_dma_BREADY;
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logic [1:0] sd_controller_dma_BRESP;
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logic sd_controller_dma_ARVALID;
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logic sd_controller_dma_ARREADY;
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logic [ADDR_WIDTH-1:0] sd_controller_dma_ARADDR;
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logic sd_controller_dma_RVALID;
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logic sd_controller_dma_RREADY;
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logic [DATA_WIDTH-1:0] sd_controller_dma_RDATA;
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logic [1:0] sd_controller_dma_RRESP;
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cpu_wrapper u_cpu_wrapper_0(
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.i_clk_cpu (clk_cpu),
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.i_clk_100 (i_sysclk),
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.i_rst (~master_reset),
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.o_cpu_rst (o_cpu0_reset),
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.o_cpu_rdy (o_cpu0_rdy),
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.o_cpu_be (),
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.o_cpu_irqb (o_cpu0_irqb),
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.o_cpu_nmib (),
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.o_cpu_sob (),
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.i_cpu_rwb (i_cpu0_rwb),
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.i_cpu_sync (i_cpu0_sync),
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.i_cpu_vpb ('0),
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.i_cpu_mlb ('0),
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.i_cpu_addr (i_cpu0_addr),
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.i_cpu_data (i_cpu0_data_from_cpu),
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.o_cpu_data (o_cpu0_data_from_dut),
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.o_AWVALID (cpu0_AWVALID),
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.i_AWREADY (cpu0_AWREADY),
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.o_AWADDR (cpu0_AWADDR),
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.o_WVALID (cpu0_WVALID),
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.i_WREADY (cpu0_WREADY),
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.o_WDATA (cpu0_WDATA),
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.o_WSTRB (cpu0_WSTRB),
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.i_BVALID (cpu0_BVALID),
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.o_BREADY (cpu0_BREADY),
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.i_BRESP (cpu0_BRESP),
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.o_ARVALID (cpu0_ARVALID),
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.i_ARREADY (cpu0_ARREADY),
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.o_ARADDR (cpu0_ARADDR),
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.i_RVALID (cpu0_RVALID),
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.o_RREADY (cpu0_RREADY),
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.i_RDATA (cpu0_RDATA),
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.i_RRESP (cpu0_RRESP),
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.i_irq('0),
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.i_nmi('0)
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);
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axi_crossbar #(
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.N_INITIATORS(2),
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.N_TARGETS(4)
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) u_crossbar (
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.clk(i_sysclk),
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.rst(~master_reset),
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.ini_araddr ({cpu0_ARADDR, sd_controller_dma_ARADDR }),
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.ini_arvalid ({cpu0_ARVALID, sd_controller_dma_ARVALID }),
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.ini_arready ({cpu0_ARREADY, sd_controller_dma_ARREADY }),
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.ini_rdata ({cpu0_RDATA, sd_controller_dma_RDATA }),
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.ini_rresp ({cpu0_RRESP, sd_controller_dma_RRESP }),
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.ini_rvalid ({cpu0_RVALID, sd_controller_dma_RVALID }),
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.ini_rready ({cpu0_RREADY, sd_controller_dma_RREADY }),
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.ini_awaddr ({cpu0_AWADDR, sd_controller_dma_AWADDR }),
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.ini_awready ({cpu0_AWREADY, sd_controller_dma_AWREADY }),
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.ini_awvalid ({cpu0_AWVALID, sd_controller_dma_AWVALID }),
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.ini_wvalid ({cpu0_WVALID, sd_controller_dma_WVALID }),
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.ini_wready ({cpu0_WREADY, sd_controller_dma_WREADY }),
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.ini_wdata ({cpu0_WDATA, sd_controller_dma_WDATA }),
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.ini_wstrb ({cpu0_WSTRB, sd_controller_dma_WSTRB }),
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.ini_bresp ({cpu0_BRESP, sd_controller_dma_BRESP }),
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.ini_bvalid ({cpu0_BVALID, sd_controller_dma_BVALID }),
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.ini_bready ({cpu0_BREADY, sd_controller_dma_BREADY }),
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.tgt_araddr ({ram_araddr, rom_araddr, sdram_ARADDR, sd_controller_csr_ARADDR }),
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.tgt_arvalid ({ram_arvalid, rom_arvalid, sdram_ARVALID, sd_controller_csr_ARVALID }),
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.tgt_arready ({ram_arready, rom_arready, sdram_ARREADY, sd_controller_csr_ARREADY }),
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.tgt_rdata ({ram_rdata, rom_rdata, sdram_RDATA, sd_controller_csr_RDATA }),
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.tgt_rresp ({ram_rresp, rom_rresp, sdram_RRESP, sd_controller_csr_RRESP }),
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.tgt_rvalid ({ram_rvalid, rom_rvalid, sdram_RVALID, sd_controller_csr_RVALID }),
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.tgt_rready ({ram_rready, rom_rready, sdram_RREADY, sd_controller_csr_RREADY }),
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.tgt_awaddr ({ram_awaddr, rom_awaddr, sdram_AWADDR, sd_controller_csr_AWADDR }),
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.tgt_awvalid ({ram_awvalid, rom_awvalid, sdram_AWVALID, sd_controller_csr_AWVALID }),
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.tgt_awready ({ram_awready, rom_awready, sdram_AWREADY, sd_controller_csr_AWREADY }),
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.tgt_wdata ({ram_wdata, rom_wdata, sdram_WDATA, sd_controller_csr_WDATA }),
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.tgt_wvalid ({ram_wvalid, rom_wvalid, sdram_WVALID, sd_controller_csr_WVALID }),
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.tgt_wready ({ram_wready, rom_wready, sdram_WREADY, sd_controller_csr_WREADY }),
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.tgt_wstrb ({ram_wstrb, rom_wstrb, sdram_WSTRB, sd_controller_csr_WSTRB }),
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.tgt_bresp ({ram_bresp, rom_bresp, sdram_BRESP, sd_controller_csr_BRESP }),
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.tgt_bvalid ({ram_bvalid, rom_bvalid, sdram_BVALID, sd_controller_csr_BVALID }),
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.tgt_bready ({ram_bready, rom_bready, sdram_BREADY, sd_controller_csr_BREADY })
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);
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axi4_lite_rom #(
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.ROM_SIZE(8),
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.ROM_INIT_FILE("init_hex.mem")
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) u_rom (
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.i_clk(i_sysclk),
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.i_rst(~master_reset),
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.o_AWREADY(rom_awready),
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.o_WREADY(rom_wready),
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.o_BVALID(rom_bvalid),
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.i_BREADY(rom_bready),
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.o_BRESP(rom_bresp),
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.i_ARVALID(rom_arvalid),
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.o_ARREADY(rom_arready),
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.i_ARADDR(rom_araddr),
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.i_ARPROT('0),
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.o_RVALID(rom_rvalid),
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.i_RREADY(rom_rready),
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.o_RDATA(rom_rdata),
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.o_RRESP(rom_rresp),
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.i_AWVALID(rom_awvalid),
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.i_AWADDR(rom_awaddr),
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.i_AWPROT('0),
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.i_WVALID(rom_wvalid),
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.i_WDATA(rom_wdata),
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.i_WSTRB(rom_wstrb)
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);
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axi4_lite_ram #(
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.RAM_SIZE(9)
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) u_ram(
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.i_clk(i_sysclk),
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.i_rst(~master_reset),
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.o_AWREADY(ram_awready),
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.o_WREADY(ram_wready),
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.o_BVALID(ram_bvalid),
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.i_BREADY(ram_bready),
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.o_BRESP(ram_bresp),
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.i_ARVALID(ram_arvalid),
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.o_ARREADY(ram_arready),
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.i_ARADDR(ram_araddr),
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.i_ARPROT('0),
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.o_RVALID(ram_rvalid),
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.i_RREADY(ram_rready),
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.o_RDATA(ram_rdata),
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.o_RRESP(ram_rresp),
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.i_AWVALID(ram_awvalid),
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.i_AWADDR(ram_awaddr),
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.i_AWPROT('0),
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.i_WVALID(ram_wvalid),
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.i_WDATA(ram_wdata),
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.i_WSTRB(ram_wstrb)
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);
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logic [1:0] w_sdr_CKE;
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logic [1:0] w_sdr_n_CS;
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logic [1:0] w_sdr_n_RAS;
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logic [1:0] w_sdr_n_CAS;
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logic [1:0] w_sdr_n_WE;
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logic [3:0] w_sdr_BA;
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logic [25:0] w_sdr_ADDR;
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logic [31:0] w_sdr_DATA;
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logic [31:0] w_sdr_DATA_oe;
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logic [3:0] w_sdr_DQM;
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assign o_sdr_CKE = w_sdr_CKE[0]; //Using SOFT ddio, ignore second cycle
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assign o_sdr_n_CS = w_sdr_n_CS[0];
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assign o_sdr_n_RAS = w_sdr_n_RAS[0];
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assign o_sdr_n_CAS = w_sdr_n_CAS[0];
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assign o_sdr_n_WE = w_sdr_n_WE[0];
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assign o_sdr_BA = w_sdr_BA[0+:2];
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assign o_sdr_ADDR = w_sdr_ADDR[0+:13];
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assign o_sdr_DATA = w_sdr_DATA[0+:16];
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assign o_sdr_DATA_oe = w_sdr_DATA_oe[0+:16];
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assign o_sdr_DQM = w_sdr_DQM[0+:2];
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sdram_controller u_sdram_controller(
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.i_aresetn (pre_reset),
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.i_sysclk (i_sysclk),
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.i_sdrclk (i_sdrclk),
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.i_tACclk (i_tACclk),
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.o_pll_reset (),
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.i_pll_locked ('1),
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.o_sdr_state (w_sdr_state),
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.i_AXI4_AWVALID (sdram_AWVALID),
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.o_AXI4_AWREADY (sdram_AWREADY),
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.i_AXI4_AWADDR (sdram_AWADDR[23:0]),
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.i_AXI4_WVALID (sdram_WVALID),
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.o_AXI4_WREADY (sdram_WREADY),
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.i_AXI4_WDATA (sdram_WDATA),
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.i_AXI4_WSTRB (sdram_WSTRB),
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.o_AXI4_BVALID (sdram_BVALID),
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.i_AXI4_BREADY (sdram_BREADY),
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.i_AXI4_ARVALID (sdram_ARVALID),
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.o_AXI4_ARREADY (sdram_ARREADY),
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.i_AXI4_ARADDR (sdram_ARADDR[23:0]),
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.o_AXI4_RVALID (sdram_RVALID),
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.i_AXI4_RREADY (sdram_RREADY),
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.o_AXI4_RDATA (sdram_RDATA),
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.i_AXI4_WLAST (sdram_WVALID),
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.o_AXI4_RLAST (),
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.i_AXI4_AWID ('0),
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.i_AXI4_AWSIZE ('0),
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.i_AXI4_ARID ('0),
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.i_AXI4_ARLEN ('0),
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.i_AXI4_ARSIZE ('0),
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.i_AXI4_ARBURST ('0),
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.i_AXI4_AWLEN ('0),
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.o_AXI4_RID (),
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.o_AXI4_BID (),
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.o_sdr_CKE (w_sdr_CKE),
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.o_sdr_n_CS (w_sdr_n_CS),
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.o_sdr_n_RAS (w_sdr_n_RAS),
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.o_sdr_n_CAS (w_sdr_n_CAS),
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.o_sdr_n_WE (w_sdr_n_WE),
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.o_sdr_BA (w_sdr_BA),
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.o_sdr_ADDR (w_sdr_ADDR),
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.o_sdr_DATA (w_sdr_DATA),
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.o_sdr_DATA_oe (w_sdr_DATA_oe),
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.i_sdr_DATA ({{16'b0}, {i_sdr_DATA}}),
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.o_sdr_DQM (w_sdr_DQM)
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);
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logic sd_controller_apb_psel;
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logic sd_controller_apb_penable;
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logic sd_controller_apb_pwrite;
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logic [2:0] sd_controller_apb_pprot;
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logic [ADDR_WIDTH-1:0] sd_controller_apb_paddr;
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logic [DATA_WIDTH-1:0] sd_controller_apb_pwdata;
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logic [DATA_WIDTH/8-1:0] sd_controller_apb_pstrb;
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logic sd_controller_apb_pready;
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logic [DATA_WIDTH-1:0] sd_controller_apb_prdata;
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logic sd_controller_apb_pslverr;
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|
|
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axi4_lite_to_apb4 u_sd_axi_apb_converter (
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.i_clk(i_sysclk),
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.i_rst(~master_reset),
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|
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.i_AWVALID(sd_controller_csr_AWVALID),
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.o_AWREADY(sd_controller_csr_AWREADY),
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.i_AWADDR(sd_controller_csr_AWADDR),
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|
.i_WVALID(sd_controller_csr_AWVALID),
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|
.o_WREADY(sd_controller_csr_WREADY),
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|
.i_WDATA(sd_controller_csr_WDATA),
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|
.i_WSTRB(sd_controller_csr_WSTRB),
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.o_BVALID(sd_controller_csr_BVALID),
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|
.i_BREADY(sd_controller_csr_BREADY),
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|
.o_BRESP(sd_controller_csr_BRESP),
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|
.i_ARVALID(sd_controller_csr_ARVALID),
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|
.o_ARREADY(sd_controller_csr_ARREADY),
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|
.i_ARADDR(sd_controller_csr_ARADDR),
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|
.i_ARPROT('0),
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|
.o_RVALID(sd_controller_csr_RVALID),
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|
.i_RREADY(sd_controller_csr_RREADY),
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|
.o_RDATA(sd_controller_csr_RDATA),
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|
.o_RRESP(sd_controller_csr_RRESP),
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|
|
|
.m_apb_psel(sd_controller_apb_psel),
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.m_apb_penable(sd_controller_apb_penable),
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|
.m_apb_pwrite(sd_controller_apb_pwrite),
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|
.m_apb_pprot(sd_controller_apb_pprot),
|
|
.m_apb_paddr(sd_controller_apb_paddr),
|
|
.m_apb_pwdata(sd_controller_apb_pwdata),
|
|
.m_apb_pstrb(sd_controller_apb_pstrb),
|
|
.m_apb_pready(sd_controller_apb_pready),
|
|
.m_apb_prdata(sd_controller_apb_prdata),
|
|
.m_apb_pslverr(sd_controller_apb_pslverr)
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|
);
|
|
|
|
endmodule |