Byron Lathi 50b0860137 Update testbench with more realistic timings ...

Updates the testbench to simulate writes with more correct timings.
Writes take two clock cycles since the cpu runs at half speed.

2022-04-10 17:50:49 -05:00

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bb_spi_testbench.sv

Add bb_spi_controller

2022-03-08 15:26:01 -06:00

crc7_testbench.sv

Add tests for crc7

2022-04-08 00:56:14 -05:00

cs_testbench.sv

Add sd card cs

2022-04-10 16:15:55 -05:00

irq_testbench.sv

Add irq status register

2022-03-14 13:16:09 -05:00

mm_testbench.sv

Fix indentation

2022-04-08 00:49:59 -05:00

sd_cmd_testbench.sv

Update testbench with more realistic timings

2022-04-10 17:50:49 -05:00

uart_testbench.sv

Add write and puts tasks to the uart testbench

2022-03-14 00:04:04 -05:00