56 lines
1.2 KiB
Systemverilog
56 lines
1.2 KiB
Systemverilog
module super6502
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(
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input [7:0] cpu_data_in,
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input cpu_sync,
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input cpu_rwb,
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input pll_in,
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input button_reset,
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input pll_cpu_locked,
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input clk_50,
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input clk_2,
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input logic [15:0] cpu_addr,
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output logic [7:0] cpu_data_out,
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output logic [7:0] cpu_data_oe,
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output logic cpu_irqb,
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output logic cpu_nmib,
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output logic cpu_rdy,
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output logic cpu_resb,
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output logic pll_cpu_reset,
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output logic cpu_phi2
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);
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assign pll_cpu_reset = '1;
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assign cpu_data_oe = {8{cpu_rwb}};
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assign cpu_rdy = '1;
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assign cpu_irqb = '1;
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assign cpu_nmib = '1;
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always @(posedge clk_2) begin
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cpu_phi2 <= ~cpu_phi2;
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end
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always @(posedge clk_2) begin
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if (button_reset == '0) begin
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cpu_resb <= '0;
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end
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else begin
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if (cpu_resb == '0) begin
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cpu_resb <= '1;
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end
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end
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end
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efx_single_port_ram boot_rom(
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.clk(clk_2), // clock input for one clock mode
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.addr(cpu_addr[7:0]), // address input
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.wclke('0), // Write clock-enable input
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.byteen('0), // Byteen input
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.we('0), // Write-enable input
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.re(cpu_rwb), // Read-enable input
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.rdata(cpu_data_out) // Read data output
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);
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endmodule
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