86 lines
1.4 KiB
Systemverilog
86 lines
1.4 KiB
Systemverilog
module testbench();
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timeunit 10ns;
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timeprecision 1ns;
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logic clk_50, clk, cs;
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logic rw, MM_cs;
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logic rst;
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logic [3:0] RS, MA;
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logic [7:0] data_in;
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logic [7:0] data_out;
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logic [11:0] MO;
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logic [11:0] _data_in;
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assign _data_in = {4'h0, data_in};
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logic [11:0] _data_out;
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assign data_out = _data_out[7:0];
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logic [15:0] cpu_addr;
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logic [23:0] mm_address;
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assign MA = cpu_addr[15:12];
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assign mm_address = {MO, cpu_addr[11:0]};
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memory_mapper dut(
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.data_in(_data_in),
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.data_out(_data_out),
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.*
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);
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always #1 clk_50 = clk_50 === 1'b0;
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always #100 clk = clk === 1'b0;
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task write_reg(logic [3:0] addr, logic [7:0] data);
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@(negedge clk);
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cs <= '1;
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RS <= addr;
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data_in <= data;
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rw <= '0;
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@(posedge clk);
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cs <= '0;
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rw <= '1;
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@(negedge clk);
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endtask
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task enable(logic [7:0] data);
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@(negedge clk);
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MM_cs <= '1;
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rw <= '0;
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data_in <= data;
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@(posedge clk);
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rw <= '1;
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MM_cs <= '0;
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@(negedge clk);
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endtask
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initial begin
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rst <= '1;
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repeat(5) @(posedge clk);
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rst <= '0;
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cpu_addr <= 16'h0abc;
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write_reg(4'h0, 8'hcc);
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$display("Address: %x", mm_address);
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assert(mm_address == 24'h000abc) else begin
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$error("Bad address before enable!");
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end
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enable(1);
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$display("Address: %x", mm_address);
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assert(mm_address == 24'h0ccabc) else begin
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$error("Bad address after enable!");
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end
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enable(0);
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$display("Address: %x", mm_address);
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assert(mm_address == 24'h000abc) else begin
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$error("Bad address after enable!");
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end
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$finish();
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end
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endmodule
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