Files
super6502/hw/efinix_fpga/simulation/Makefile
Byron Lathi 5e03795c09 Get something simulated
Infinite loop being caused somewhere
2023-09-21 23:22:17 -07:00

22 lines
479 B
Makefile

SRCS=$(shell find src/ -type f -name "*.*v")
SRCS+=$(shell find ../ip/ -type f -name "*.*v" -not \( -name "*tmpl*" \))
SRCS+=$(shell find ../src/ -type f -name "*.*v")
INC=$(shell find include/ -type f)
#TODO implement something like sources.list
TOP_MODULE=sim_top
TARGET=sim_top
INIT_MEM=init_hex.mem
all: $(INIT_MEM)
iverilog -g2005-sv -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
$(INIT_MEM):
cp ../$(INIT_MEM) .
.PHONY: clean
clean:
rm -rf $(TARGET)
rm $(INIT_MEM)