5f6657a227
Adds a 16x16 divider to go with the multiplier. The divider is a single stage with no pipelining, which works at the slow 2MHz frequency. Doing this lowers the maximum clock frequency to 5. This is acceptable for now but means that the cpu can't be run at 14, which is the maximum frequency.
82 lines
1.2 KiB
Systemverilog
82 lines
1.2 KiB
Systemverilog
module divider_wrapper(
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input clk,
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input reset,
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input [7:0] i_data,
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output logic [7:0] o_data,
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input cs,
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input rwb,
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input [2:0] addr
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);
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logic [15:0] numer, denom;
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logic [15:0] quotient, remain;
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logic clken, rfd;
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assign clken = '1;
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divider u_divider(
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.numer ( numer ),
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.denom ( denom ),
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.clken ( clken ),
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.clk ( clk ),
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.reset ( reset ),
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.quotient ( quotient ),
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.remain ( remain ),
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.rfd ( rfd )
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);
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always_ff @(negedge clk) begin
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if (reset) begin
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numer <= '0;
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denom <= '0;
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end
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if (cs & ~rwb) begin
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case (addr)
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3'h0: begin
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numer[7:0] <= i_data;
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end
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3'h1: begin
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numer[15:8] <= i_data;
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end
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3'h2: begin
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denom[7:0] <= i_data;
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end
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3'h3: begin
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denom[15:8] <= i_data;
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end
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endcase
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end
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end
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always_comb begin
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case (addr)
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3'h4: begin
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o_data = quotient[7:0];
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end
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3'h5: begin
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o_data = quotient[15:8];
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end
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3'h6: begin
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o_data = remain[7:0];
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end
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3'h7: begin
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o_data = remain[15:8];
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end
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endcase
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end
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endmodule |