5f6657a227
Adds a 16x16 divider to go with the multiplier. The divider is a single stage with no pipelining, which works at the slow 2MHz frequency. Doing this lowers the maximum clock frequency to 5. This is acceptable for now but means that the cpu can't be run at 14, which is the maximum frequency.
50 lines
3.4 KiB
Systemverilog
50 lines
3.4 KiB
Systemverilog
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function [255:0] bram_ini_table;
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input integer index;//Mode type
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input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved
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case (index)
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0: bram_ini_table=
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(val_== 0)?256'h008d0000d000a9000ef000e90008d00001000a9000ef000e80008d000c8000a9:
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(val_== 1)?256'h0ef000ff0008d000ef000ec000ad000ef000eb0008d00000000a9000ef000ea0:
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(val_== 2)?256'h00000000000000000000000000000000000000000000000000e300080000cb00:
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(val_== 3)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_== 4)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_== 5)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_== 6)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_== 7)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_== 8)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_== 9)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==10)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==11)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==12)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==13)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==14)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==15)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==16)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==17)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==18)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==19)?256'h000ff00000000ff00000000ff000000000000000000000000000000000000000:
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(val_==20)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==21)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==22)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==23)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==24)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==25)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==26)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==27)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==28)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==29)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==30)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==31)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==32)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==33)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==34)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==35)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==36)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==37)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==38)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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(val_==39)?256'h0000000000000000000000000000000000000000000000000000000000000000:
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0;
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endcase
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endfunction
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