Files
super6502/hw/efinix_fpga/ip/bram/init_hex.mem
Byron Lathi 5f6657a227 Add divider
Adds a 16x16 divider to go with the multiplier.

The divider is a single stage with no pipelining, which works at the
slow 2MHz frequency. Doing this lowers the maximum clock frequency to 5.

This is acceptable for now but means that the cpu can't be run at 14,
which is the maximum frequency.
2023-01-05 18:35:42 -05:00

257 lines
768 B
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