5f6657a227
Adds a 16x16 divider to go with the multiplier. The divider is a single stage with no pipelining, which works at the slow 2MHz frequency. Doing this lowers the maximum clock frequency to 5. This is acceptable for now but means that the cpu can't be run at 14, which is the maximum frequency.
101 lines
6.8 KiB
XML
101 lines
6.8 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<efx:project name="super6502" description="" last_change_date="Thu January 5 2023 18:30:12" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
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<efx:device_info>
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<efx:family name="Trion"/>
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<efx:device name="T20F256"/>
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<efx:timing_model name="C4"/>
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</efx:device_info>
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<efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008">
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<efx:top_module name="super6502"/>
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<efx:design_file name="super6502.sv" version="default" library="default"/>
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<efx:design_file name="ip/bram/bram_primitive.v" version="verilog_2k" library="default"/>
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<efx:design_file name="ip/bram/bram_decompose.vh" version="verilog_2k" library="default"/>
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<efx:design_file name="ip/bram/bram_ini.vh" version="verilog_2k" library="default"/>
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<efx:design_file name="ip/bram/efx_single_port_ram.v" version="verilog_2k" library="default"/>
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<efx:design_file name="ip/bram/bram_wrapper_mwm.v" version="verilog_2k" library="default"/>
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<efx:design_file name="leds.sv" version="default" library="default"/>
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<efx:design_file name="addr_decode.sv" version="default" library="default"/>
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<efx:design_file name="sdram_adapter.sv" version="default" library="default"/>
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<efx:design_file name="timer.sv" version="default" library="default"/>
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<efx:design_file name="interrupt_controller.sv" version="default" library="default"/>
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<efx:design_file name="multiplier.sv" version="default" library="default"/>
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<efx:design_file name="divider_wrapper.sv" version="default" library="default"/>
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<efx:top_vhdl_arch name=""/>
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</efx:design_info>
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<efx:constraint_info>
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<efx:sdc_file name="super6502.pt.sdc"/>
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<efx:inter_file name=""/>
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</efx:constraint_info>
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<efx:sim_info/>
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<efx:misc_info/>
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<efx:ip_info>
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<efx:ip instance_name="sdram_controller" path="ip/sdram_controller/settings.json">
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<efx:ip_src_file name="sdram_controller.v"/>
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</efx:ip>
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<efx:ip instance_name="divider" path="ip/divider/settings.json">
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<efx:ip_src_file name="divider.v"/>
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</efx:ip>
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</efx:ip_info>
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<efx:synthesis tool_name="efx_map">
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<efx:param name="work_dir" value="work_syn" value_type="e_string"/>
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<efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
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<efx:param name="mode" value="speed" value_type="e_option"/>
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<efx:param name="max_ram" value="-1" value_type="e_integer"/>
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<efx:param name="max_mult" value="-1" value_type="e_integer"/>
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<efx:param name="infer-clk-enable" value="3" value_type="e_option"/>
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<efx:param name="infer-sync-set-reset" value="1" value_type="e_option"/>
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<efx:param name="fanout-limit" value="0" value_type="e_integer"/>
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<efx:param name="bram_output_regs_packing" value="1" value_type="e_option"/>
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<efx:param name="retiming" value="1" value_type="e_option"/>
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<efx:param name="seq_opt" value="1" value_type="e_option"/>
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<efx:param name="blast_const_operand_adders" value="1" value_type="e_option"/>
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<efx:param name="operator-sharing" value="0" value_type="e_option"/>
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<efx:param name="optimize-adder-tree" value="0" value_type="e_option"/>
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<efx:param name="mult_input_regs_packing" value="1" value_type="e_option"/>
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<efx:param name="mult_output_regs_packing" value="1" value_type="e_option"/>
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<efx:param name="min-sr-fanout" value="0" value_type="e_option"/>
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<efx:param name="seq-opt-sync-only" value="0" value_type="e_option"/>
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<efx:param name="blackbox-error" value="1" value_type="e_option"/>
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<efx:param name="allow-const-ram-index" value="0" value_type="e_option"/>
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<efx:param name="hdl-compile-unit" value="1" value_type="e_option"/>
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<efx:param name="create-onehot-fsms" value="0" value_type="e_option"/>
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<efx:param name="min-ce-fanout" value="0" value_type="e_integer"/>
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<efx:param name="include" value="ip/sdram_controller" value_type="e_string"/>
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<efx:param name="include" value="ip/divider" value_type="e_string"/>
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</efx:synthesis>
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<efx:place_and_route tool_name="efx_pnr">
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<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
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<efx:param name="verbose" value="off" value_type="e_bool"/>
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<efx:param name="load_delaym" value="on" value_type="e_bool"/>
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<efx:param name="optimization_level" value="NULL" value_type="e_option"/>
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<efx:param name="seed" value="1" value_type="e_integer"/>
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<efx:param name="placer_effort_level" value="2" value_type="e_option"/>
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<efx:param name="max_threads" value="-1" value_type="e_integer"/>
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</efx:place_and_route>
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<efx:bitstream_generation tool_name="efx_pgm">
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<efx:param name="mode" value="active" value_type="e_option"/>
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<efx:param name="width" value="1" value_type="e_option"/>
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<efx:param name="enable_roms" value="smart" value_type="e_option"/>
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<efx:param name="spi_low_power_mode" value="on" value_type="e_bool"/>
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<efx:param name="io_weak_pullup" value="on" value_type="e_bool"/>
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<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option"/>
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<efx:param name="bitstream_compression" value="off" value_type="e_bool"/>
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<efx:param name="enable_external_master_clock" value="off" value_type="e_bool"/>
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<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option"/>
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<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string"/>
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<efx:param name="release_tri_then_reset" value="on" value_type="e_bool"/>
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<efx:param name="cold_boot" value="off" value_type="e_bool"/>
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<efx:param name="cascade" value="off" value_type="e_option"/>
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<efx:param name="generate_bit" value="on" value_type="e_bool"/>
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<efx:param name="generate_bitbin" value="off" value_type="e_bool"/>
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<efx:param name="generate_hex" value="on" value_type="e_bool"/>
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<efx:param name="generate_hexbin" value="off" value_type="e_bool"/>
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<efx:param name="four_byte_addressing" value="off" value_type="e_bool"/>
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</efx:bitstream_generation>
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<efx:debugger>
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<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
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<efx:param name="auto_instantiation" value="on" value_type="e_bool"/>
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<efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string"/>
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</efx:debugger>
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</efx:project>
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