5f6657a227
Adds a 16x16 divider to go with the multiplier. The divider is a single stage with no pipelining, which works at the slow 2MHz frequency. Doing this lowers the maximum clock frequency to 5. This is acceptable for now but means that the cpu can't be run at 14, which is the maximum frequency.
20 lines
365 B
Makefile
20 lines
365 B
Makefile
TARGETS=stacktest runram timer timer_irq multiplier divider
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SRC=$(wildcard *.s)
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DIR=../ip/bram
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all: $(TARGETS)
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$(TARGETS): $(SRC)
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cl65 --cpu 65c02 -C link.ld -l $@.list $@.s
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xxd -ps $@ | fold -w 2 > $@.hex
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install:
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cp $(TARGET).hex $(DIR)/init_hex.mem
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cd $(DIR);python3 efx_mem_init_script.py hex init_hex.mem
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clean:
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rm -f $(TARGETS)
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rm *.hex
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rm *.list
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