56 lines
1.2 KiB
Systemverilog
56 lines
1.2 KiB
Systemverilog
module mapper(
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input clk,
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input rst,
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input [15:0] cpu_addr,
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output logic [24:0] sdram_addr,
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input cs,
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input rwb,
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input [7:0] i_data,
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output logic [7:0] o_data
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);
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logic [12:0] map [16];
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logic [15:0] base_addr;
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assign base_addr = cpu_addr - 16'hefb7;
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logic en;
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always_comb begin
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if (!en) begin
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sdram_addr = {9'b0, cpu_addr};
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end else begin
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sdram_addr = {map[cpu_addr[15:12]], cpu_addr[11:0]};
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end
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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en <= '0;
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for (bit [13:0] a = 14'b0; a < 14'h10; a++) begin
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map[a] = a;
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end
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end else begin
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if (~rwb & cs) begin
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if (base_addr == 16'h32) begin
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en <= i_data[0];
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end else begin
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if (!base_addr[0]) begin
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map[base_addr[3:1]] <= {i_data[5:0], map[base_addr[3:1]][7:0]};
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end else begin
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map[base_addr[3:1]] <= {map[base_addr[3:1]][12:8], i_data};
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end
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end
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end
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end
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end
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// each each entry is 4k and total address space is 64M,
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// so we need 2^14 possible entries
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endmodule
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