61f6e53327
1. in SD mode, CMD0 does not have a response, so we specifically ignore it. 2. The penable signal was messed up, although it looks like this doesn't matter anyway 3. The SD clock should be out of phase from the data signal by 180 degrees, so that we get max hold time
32 lines
508 B
ArmAsm
32 lines
508 B
ArmAsm
.export _init, _nmi_int, _irq_int
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.segment "VECTORS"
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.addr _nmi_int ; NMI vector
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.addr _init ; Reset vector
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.addr _irq_int ; IRQ/BRK vector
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SD_CONTROLLER = $e000
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SD_ARG = SD_CONTROLLER + $4
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CLK_DIV = $20
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.code
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_nmi_int:
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_irq_int:
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_init:
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lda #$00
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sta SD_CONTROLLER
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lda #$aa
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sta SD_ARG
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lda #$01
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sta SD_ARG+1
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lda #$00
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sta SD_ARG+2
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sta SD_ARG+3
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lda #$08
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sta SD_CONTROLLER
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@end: bra @end
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