274 lines
8.9 KiB
Systemverilog
274 lines
8.9 KiB
Systemverilog
module sdram_adapter(
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input logic i_cpuclk,
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input logic i_arst, // Async Reset
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input logic i_sysclk, // Controller Clock (100MHz)
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input logic i_sdrclk, // t_su and t_wd clock (200MHz)
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input logic i_tACclk, // t_ac clock (200MHz)
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input logic i_cs, // Chip select
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input logic i_rwb, // Read/Write. Write is low
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input logic [24:0] i_addr, // Input address. Byte addressed
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input logic [7:0] i_data, // Input Data
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output logic [7:0] o_data, // Output data
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output o_sdr_init_done,
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output o_sdr_CKE,
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output o_sdr_n_CS,
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output o_sdr_n_RAS,
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output o_sdr_n_CAS,
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output o_sdr_n_WE,
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output [1:0] o_sdr_BA,
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output [12:0] o_sdr_ADDR,
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output [15:0] o_sdr_DATA,
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output [15:0] o_sdr_DATA_oe,
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input [15:0] i_sdr_DATA,
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output [1:0] o_sdr_DQM
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);
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logic [1:0] w_sdr_CKE;
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logic [1:0] w_sdr_n_CS;
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logic [1:0] w_sdr_n_RAS;
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logic [1:0] w_sdr_n_CAS;
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logic [1:0] w_sdr_n_WE;
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logic [3:0] w_sdr_BA;
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logic [25:0] w_sdr_ADDR;
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logic [31:0] w_sdr_DATA;
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logic [31:0] w_sdr_DATA_oe;
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logic [3:0] w_sdr_DQM;
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assign o_sdr_CKE = w_sdr_CKE[0]; //Using SOFT ddio, ignore second cycle
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assign o_sdr_n_CS = w_sdr_n_CS[0];
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assign o_sdr_n_RAS = w_sdr_n_RAS[0];
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assign o_sdr_n_CAS = w_sdr_n_CAS[0];
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assign o_sdr_n_WE = w_sdr_n_WE[0];
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assign o_sdr_BA = w_sdr_BA[0+:2];
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assign o_sdr_ADDR = w_sdr_ADDR[0+:13];
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assign o_sdr_DATA = w_sdr_DATA[0+:16];
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assign o_sdr_DATA_oe = w_sdr_DATA_oe[0+:16];
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assign o_sdr_DQM = w_sdr_DQM[0+:2];
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// What should happen when the cpu writes something?
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// 1. Address should already be calculated from the memory mapper, don't need to worry about it
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// 2. Data byte position needs to be determined. Each write is 32 bits, so the dm bits need to
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// be set and the byte shifted to the correct position
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// 3. write enable and last should be set high. Only ever do bursts of 1.
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// 4. Sample wr_ack and when it goes high, release write_enable and last
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// What should happen when the cpu reads something?
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// 1. Address should already be calculated from the memory mapper, don't need to worry about it
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// 2. read_enable and last should be set high. Only ever to bursts of 1.
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// 3. Sample rd_ack and when it goes high, release read_enable and last
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// 4. Sample read_valid signal. When it is high, grab the data on the on the bus.
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// The returned data will be 16 bit, so you need to extract the correct byte. (or will it be 32?)
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// when writing, the write data is only valid on a falling edge.
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// Really all of this should be done on falling edges.
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// But basically if we are in access, and cpuclk goes low, go back to wait.
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// If something actually happened, we would be in one of the read/write states.
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enum bit [1:0] {ACCESS, READ_WAIT, WRITE_WAIT, WAIT} state, next_state;
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logic w_read, w_write, w_last;
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logic [23:0] w_addr, r_addr;
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logic [31:0] w_data_i, w_data_o;
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logic [3:0] w_dm, r_dm;
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logic w_wr_ack, w_rd_ack, w_rd_valid;
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logic [7:0] data, _data;
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logic w_data_valid;
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logic [31:0] r_write_data;
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logic [1:0] counter, next_counter;
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always @(posedge i_sysclk) begin
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if (i_arst) begin
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state <= WAIT;
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counter <= '0;
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end else begin
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state <= next_state;
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counter <= next_counter;
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r_write_data <= w_data_i;
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r_addr <= w_addr;
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r_dm <= w_dm;
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end
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if (w_data_valid)
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o_data <= _data;
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end
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//because of timing issues, We really need to trigger
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//the write on the falling edge of phi2. There is a 2ns
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//delay between the rising edge of phi2 and data valid
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//Since the address is valid on the previous falling edge,
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//Reads can occur on the rising edge I guess.
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//so basically cpu clock goes high when cs goes high we go into a priming state
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//where we wait until cs goes low. when cpu clock is low, do the actual write.
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//in terms of the existing state, the access state needs to only do something
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//if selected AND cpu_clock is low. If cpu clock is high, we should be in wait,
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//and after the read/write is complete we should also go back to wait.
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//actually that may only apply to writes, since reads should occur at the rising
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//edge of i_cpuclk
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//Starts out in state 0 with cpuclk low and cs high.
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//Then, cpuclk goes high. This is now a valid time to read
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//After this, cpuclk goes low again, this is now a valid time to write.
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//so basically if cpuclk goes low when cs is low, go to wait state
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//what I am thinking is basically 2 states like before. wait and access.
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//we go to access when cpuclk is high and cs is high.
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//we can read as soon as we want if rwn is high.
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//BUT if rwb is low then we have to wait untl cpuclk goes low again.
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always_comb begin
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next_state = state;
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next_counter = counter;
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w_addr = '0;
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w_dm = '0;
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w_read = '0;
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w_write = '0;
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w_last = '0;
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w_data_i = '0;
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w_data_valid = '0;
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_data = 0;
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unique case (state)
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WAIT: begin
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if (i_cs & i_cpuclk)
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next_state = ACCESS;
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end
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ACCESS: begin
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// only do something if selected
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if (i_cs) begin
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w_addr = {{i_addr[24:2]}, {1'b0}};; // divide by 2, set last bit to 0
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if (i_rwb) begin //read
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w_read = '1;
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w_last = '1;
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// dm is not needed for reads?
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if (w_rd_ack) next_state = READ_WAIT;
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end else begin //write
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w_data_i = i_data << (8*i_addr[1:0]);
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//w_data_i = {4{i_data}}; //does anything get through?
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w_dm = ~(4'b1 << i_addr[1:0]);
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if (~i_cpuclk) begin
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w_write = '1;
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w_last = '1;
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next_state = WRITE_WAIT;
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end
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end
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end
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end
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WRITE_WAIT: begin
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// stay in this state until write is acknowledged.
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w_write = '1;
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w_last = '1;
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w_data_i = r_write_data;
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w_dm = r_dm;
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w_addr = r_addr;
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if (w_wr_ack) next_state = WAIT;
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end
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READ_WAIT: begin
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if (w_rd_valid) begin
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w_data_valid = '1;
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_data = w_data_o[8*i_addr[1:0]+:8];
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end
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// you must wait until the next cycle!
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if (~i_cpuclk) begin
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next_state = WAIT;
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end
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end
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endcase
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end
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//this seems scuffed
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logic [23:0] addr_mux_out;
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always_comb begin
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if (state == ACCESS) begin
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addr_mux_out = w_addr;
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end else begin
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addr_mux_out = r_addr;
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end
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end
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logic o_dbg_tRTW_done;
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logic o_dbg_ref_req;
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logic o_dbg_wr_ack;
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logic o_dbg_rd_ack;
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logic [1:0] o_dbg_n_CS;
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logic [1:0] o_dbg_n_RAS;
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logic [1:0] o_dbg_n_CAS;
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logic [1:0] o_dbg_n_WE;
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logic [3:0] o_dbg_BA;
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logic [25:0] o_dbg_ADDR;
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logic [31:0] o_dbg_DATA_out;
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logic [31:0] o_dbg_DATA_in;
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logic o_sdr_init_done;
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logic [3:0] o_sdr_state;
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sdram_controller u_sdram_controller(
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.i_arst(i_arst), //Positive Controller Reset
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.i_sysclk(i_sysclk), //Controller Clock (100MHz)
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.i_sdrclk(i_sdrclk), //t_su and t_ac clock. Double sysclk (200MHz)
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.i_tACclk(i_tACclk), //t_ac clock. Also double sysclk, but different pll for tuning
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.i_pll_locked(1'b1), //There exists a pll locked output from the pll, not sure why they don't use it.
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.i_we(w_write), //Write enable. Can only be de-asserted if i_last is asserted and o_wr_ack is sampled high.
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.i_re(w_read), //Read enable. Can only be de-asserted if i_last is asserted and o_rd_ack is sampled high.
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.i_last(w_last), //Set to high to indicate the last transfer of a burst write or read.
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.i_addr(addr_mux_out), //SDRAM physical address B R C. For half rate, only even addresses.
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.i_din(r_write_data), //Data to write to SDRAM. Twice normal width when running at half speed (hence the even addresses)
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.i_dm(r_dm), //dm (r_dm)
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.o_dout(w_data_o), //Data read from SDRAM, doubled as above.
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.o_sdr_init_done(o_sdr_init_done), //Indicates that the SDRAM initialization is done.
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.o_wr_ack(w_wr_ack), //Write acknowledge, handshake with we
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.o_rd_ack(w_rd_ack), //Read acknowledge, handshake with re
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.o_rd_valid(w_rd_valid),//Read valid. The data on o_dout is valid
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.o_sdr_CKE(w_sdr_CKE),
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.o_sdr_n_CS(w_sdr_n_CS),
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.o_sdr_n_RAS(w_sdr_n_RAS),
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.o_sdr_n_CAS(w_sdr_n_CAS),
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.o_sdr_n_WE(w_sdr_n_WE),
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.o_sdr_BA(w_sdr_BA),
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.o_sdr_ADDR(w_sdr_ADDR),
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.o_sdr_DATA(w_sdr_DATA),
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.o_sdr_DATA_oe(w_sdr_DATA_oe),
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.i_sdr_DATA({{16'b0}, {i_sdr_DATA}}),
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.o_sdr_DQM(w_sdr_DQM),
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//Does include debug signals.
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.o_sdr_state(o_sdr_state),
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.o_dbg_tRTW_done ( o_dbg_tRTW_done ),
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.o_dbg_ref_req ( o_dbg_ref_req ),
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.o_dbg_wr_ack ( o_dbg_wr_ack ),
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.o_dbg_rd_ack ( o_dbg_rd_ack ),
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.o_dbg_n_CS ( o_dbg_n_CS ),
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.o_dbg_n_RAS ( o_dbg_n_RAS ),
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.o_dbg_n_CAS ( o_dbg_n_CAS ),
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.o_dbg_n_WE ( o_dbg_n_WE ),
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.o_dbg_BA ( o_dbg_BA ),
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.o_dbg_ADDR ( o_dbg_ADDR ),
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.o_dbg_DATA_out ( o_dbg_DATA_out ),
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.o_dbg_DATA_in ( o_dbg_DATA_in )
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);
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endmodule
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