bslathi19/super6502
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
7682dffe3c95837c93e199971c88214df28376a8
super6502/hw/efinix_fpga
History
Byron Lathi 7682dffe3c Change test program to use correct args 
Seems to work, when you run the test program it resets the card and
sends the voltage and test pattern, and it does receive a response from
the card.
2023-01-12 21:45:13 -06:00
..
ip
Change test program to use correct args
2023-01-12 21:45:13 -06:00
simulation
Create interrupt controller
2023-01-03 14:50:45 -05:00
test_programs
Change test program to use correct args
2023-01-12 21:45:13 -06:00
.gitignore
Add timer and testbench
2022-12-29 11:14:32 -05:00
addr_decode.sv
Add files from previous version
2023-01-12 17:06:25 -06:00
crc7.sv
Add files from previous version
2023-01-12 17:06:25 -06:00
debug_profile.wizard.json
Change test program to use correct args
2023-01-12 21:45:13 -06:00
divider_wrapper.sv
Change divider to pipelined version
2023-01-05 19:21:00 -05:00
interrupt_controller.sv
Create interrupt controller
2023-01-03 14:50:45 -05:00
leds.sv
change to asynchronous read
2022-12-29 11:51:07 -05:00
multiplier.sv
Add multiplier
2023-01-04 16:15:02 -05:00
sd_controller.sv
Add files from previous version
2023-01-12 17:06:25 -06:00
sdram_adapter.sv
Add back in DM signals for proper byte accesses
2022-12-22 23:26:01 -05:00
super6502.peri.xml
Add weak pull up (NEED STRONGER PULLUP)
2023-01-12 17:05:06 -06:00
super6502.pt.sdc
First stab at getting sdram working
2022-12-22 20:25:32 -05:00
super6502.sv
Add files from previous version
2023-01-12 17:06:25 -06:00
super6502.xml
Change test program to use correct args
2023-01-12 21:45:13 -06:00
timer.sv
Add interrupt based timer and test code
2023-01-03 18:20:34 -05:00
uart_wrapper.sv
Add write flag and reset logic for read flag
2023-01-12 14:04:44 -06:00