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super6502/hw/fpga/super6502.sdc
Byron Lathi 3d9d340520 Get the FPGA part working
This changes some of the clocks, fixes a bug in the seven segment stuff.
2022-03-11 22:55:26 -06:00

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#**************************************************************
# Create Clock (where clk is the user-defined system clock name)
#**************************************************************
create_clock -name {clk_50} -period 20ns -waveform {0.000 5.000} [get_ports {clk}]
# Constrain the input I/O path
set_input_delay -clock {clk} -max 3 [all_inputs]
set_input_delay -clock {clk} -min 2 [all_inputs]
# Constrain the output I/O path
set_output_delay -clock {clk} 2 [all_outputs]
derive_clock_uncertainty