49 lines
1.0 KiB
Systemverilog
49 lines
1.0 KiB
Systemverilog
`timescale 1ns/1ps
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module rtc_code_tb();
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sim_top u_sim_top();
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always begin
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if (
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u_sim_top.w_cpu_addr == 16'h0 &&
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u_sim_top.w_cpu_we == '1
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) begin
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if (u_sim_top.w_cpu_data_from_cpu == 8'h6d) begin
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$display("Good finish!");
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$finish();
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end else begin
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$display("Bad finish!");
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$finish_and_return(-1);
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end
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end
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# 1;
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end
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localparam increment = 3;
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logic [7:0] prev;
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initial prev = '0;
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always @(u_sim_top.w_cpu_addr) begin
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if (
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u_sim_top.w_cpu_addr == 16'h1 &&
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u_sim_top.w_cpu_we == '1
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) begin
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if (u_sim_top.w_cpu_data_from_cpu <= prev) begin
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$display("Value didn't increment!");
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$display("Bad finish!");
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$finish_and_return(-1);
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end
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prev = u_sim_top.w_cpu_data_from_cpu;
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$display("print1: %x", u_sim_top.w_cpu_data_from_cpu);
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end
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end
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initial begin
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repeat (5000) @(posedge u_sim_top.r_clk_cpu);
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$display("Timed out");
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$finish_and_return(-1);
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end
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endmodule |