77 lines
3.6 KiB
VHDL
77 lines
3.6 KiB
VHDL
////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
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//
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// This document contains proprietary information which is
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// protected by copyright. All rights are reserved. This notice
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// refers to original work by Efinix, Inc. which may be derivitive
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// of other work distributed under license of the authors. In the
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// case of derivative work, nothing in this notice overrides the
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// original author's license agreement. Where applicable, the
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// original license agreement is included in it's original
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// unmodified form immediately below this header.
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//
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// WARRANTY DISCLAIMER.
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// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
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// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
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// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
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// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
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// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
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// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
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// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
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//
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// LIMITATION OF LIABILITY.
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// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
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// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
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// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
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// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
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// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
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// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
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// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
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// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
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// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
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// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
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// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
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// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
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// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
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// APPLY TO LICENSEE.
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//
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////////////////////////////////////////////////////////////////////////////////
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------------- Begin Cut here for COMPONENT Declaration ------
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COMPONENT uart is
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PORT (
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tx_o : out std_logic;
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rx_i : in std_logic;
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tx_busy : out std_logic;
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rx_data : out std_logic_vector(7 downto 0);
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rx_data_valid : out std_logic;
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rx_error : out std_logic;
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rx_parity_error : out std_logic;
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rx_busy : out std_logic;
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baud_x16_ce : out std_logic;
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clk : in std_logic;
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reset : in std_logic;
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tx_data : in std_logic_vector(7 downto 0);
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baud_rate : in std_logic_vector(2 downto 0);
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tx_en : in std_logic);
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END COMPONENT;
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---------------------- End COMPONENT Declaration ------------
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------------- Begin Cut here for INSTANTIATION Template -----
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u_uart : uart
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PORT MAP (
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tx_o => tx_o,
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rx_i => rx_i,
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tx_busy => tx_busy,
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rx_data => rx_data,
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rx_data_valid => rx_data_valid,
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rx_error => rx_error,
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rx_parity_error => rx_parity_error,
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rx_busy => rx_busy,
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baud_x16_ce => baud_x16_ce,
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clk => clk,
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reset => reset,
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tx_data => tx_data,
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baud_rate => baud_rate,
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tx_en => tx_en);
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------------------------ End INSTANTIATION Template ---------
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