8181a3a583
The pipelining allows the cpu to run at a faster clock speed but results in latency. At the current 2 MHz, there is 1 cycle of latency which is negligible because the 6502 cannot do sequential data memory accesses. In the future, there will have to be some sort of status flag or interrupt showing that the divider is ready.
92 lines
1.4 KiB
Systemverilog
92 lines
1.4 KiB
Systemverilog
module divider_wrapper(
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input clk,
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input divclk,
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input reset,
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input [7:0] i_data,
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output logic [7:0] o_data,
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input cs,
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input rwb,
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input [2:0] addr
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);
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logic [15:0] numer, denom;
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logic [15:0] quotient, remain;
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logic [15:0] r_quotient, r_remain;
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logic clken, rfd;
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assign clken = '1;
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divider u_divider(
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.numer ( numer ),
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.denom ( denom ),
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.clken ( clken ),
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.clk ( divclk ),
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.reset ( reset ),
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.quotient ( quotient ),
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.remain ( remain ),
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.rfd ( rfd )
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);
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always_ff @(negedge clk) begin
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if (reset) begin
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numer <= '0;
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denom <= '0;
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end
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if (cs & ~rwb) begin
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case (addr)
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3'h0: begin
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numer[7:0] <= i_data;
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end
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3'h1: begin
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numer[15:8] <= i_data;
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end
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3'h2: begin
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denom[7:0] <= i_data;
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end
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3'h3: begin
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denom[15:8] <= i_data;
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end
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endcase
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end
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end
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always_ff @(posedge divclk) begin
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if (rfd) begin
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r_quotient <= quotient;
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r_remain <= remain;
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end
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end
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always_comb begin
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case (addr)
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3'h4: begin
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o_data = r_quotient[7:0];
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end
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3'h5: begin
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o_data = r_quotient[15:8];
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end
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3'h6: begin
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o_data = r_remain[7:0];
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end
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3'h7: begin
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o_data = r_remain[15:8];
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end
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endcase
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end
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endmodule |