8181a3a583
The pipelining allows the cpu to run at a faster clock speed but results in latency. At the current 2 MHz, there is 1 cycle of latency which is negligible because the 6502 cannot do sequential data memory accesses. In the future, there will have to be some sort of status flag or interrupt showing that the divider is ready.
391 lines
14 KiB
Verilog
391 lines
14 KiB
Verilog
// =============================================================================
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// Generated by efx_ipmgr
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// Version: 2022.2.322
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// IP Version: 2.2
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// =============================================================================
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
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//
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// This document contains proprietary information which is
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// protected by copyright. All rights are reserved. This notice
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// refers to original work by Efinix, Inc. which may be derivitive
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// of other work distributed under license of the authors. In the
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// case of derivative work, nothing in this notice overrides the
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// original author's license agreement. Where applicable, the
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// original license agreement is included in it's original
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// unmodified form immediately below this header.
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//
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// WARRANTY DISCLAIMER.
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// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
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// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
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// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
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// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
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// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
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// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
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// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
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//
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// LIMITATION OF LIABILITY.
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// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
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// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
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// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
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// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
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// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
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// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
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// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
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// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
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// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
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// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
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// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
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// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
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// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
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// APPLY TO LICENSEE.
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//
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////////////////////////////////////////////////////////////////////////////////
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`define IP_UUID _e54826097db04c8995c0c56653e54765
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`define IP_NAME_CONCAT(a,b) a``b
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`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
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module divider (
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input [15:0] numer,
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input [15:0] denom,
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input clken,
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input clk,
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input reset,
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output [15:0] quotient,
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output [15:0] remain,
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output rfd
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);
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`IP_MODULE_NAME(divider) #(
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.NREPRESENTATION ("UNSIGNED"),
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.WIDTHN (16),
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.WIDTHD (16),
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.DREPRESENTATION ("UNSIGNED"),
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.PIPELINE (0),
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.LATENCY (16)
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) u_divider(
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.numer ( numer ),
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.denom ( denom ),
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.clken ( clken ),
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.clk ( clk ),
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.reset ( reset ),
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.quotient ( quotient ),
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.remain ( remain ),
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.rfd ( rfd )
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);
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endmodule
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`timescale 1ns / 1ps
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module `IP_MODULE_NAME(divider) (
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clk,
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reset,
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numer,
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denom,
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quotient,
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remain,
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rfd,
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clken
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);
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parameter WIDTHN = 8;
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parameter WIDTHD = 8;
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parameter LATENCY = 8;
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parameter PIPELINE = 1;
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parameter NREPRESENTATION = "UNSIGNED";
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parameter DREPRESENTATION = "UNSIGNED";
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parameter ENABLE_OUTREG = 0;
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input clk;
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input reset;
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input clken;
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input [(WIDTHN-1):0] numer;
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input [(WIDTHD-1):0] denom;
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//output
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output reg rfd;
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output reg [(WIDTHN-1):0] quotient;
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output reg [(WIDTHD-1):0] remain;
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wire [WIDTHN-1:0] numer_temp;
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wire [WIDTHD-1:0] denom_temp;
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wire sign_numer;
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wire sign_denom;
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wire [(WIDTHN-1):0] quotient_copy;
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wire [(WIDTHD-1):0] remain_copy;
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reg sign_quotient[LATENCY:0];
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genvar i, j;
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// Main operation
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generate begin
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if(NREPRESENTATION == "SIGNED") begin
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assign numer_temp = (numer[(WIDTHN-1)] == 1'b1) ? (~numer + 1) : numer;
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assign sign_numer = (numer[(WIDTHN-1)] == 1'b1) ? 1'b1 : 1'b0;
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end
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else begin
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assign numer_temp = numer;
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assign sign_numer = 1'b0;
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end
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if(DREPRESENTATION == "SIGNED") begin
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assign denom_temp = (denom[(WIDTHD-1)] == 1'b1) ? (~denom + 1) : denom;
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assign sign_denom = (denom[(WIDTHD-1)] == 1'b1) ? 1'b1 : 1'b0;
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end
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else begin
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assign denom_temp = denom;
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assign sign_denom = 1'b0;
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end
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always @* begin
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sign_quotient[0] = sign_numer ^ sign_denom;
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end
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for (i=0; i<LATENCY; i=i+1) begin
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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sign_quotient[i+1] <= 1'b0;
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end
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else if(clken) begin
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sign_quotient[i+1] <= sign_quotient[i];
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end
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end
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end
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if (PIPELINE) begin : pipeline
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wire [(WIDTHN+1):0] sub[WIDTHN-1:0];
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reg [WIDTHN-1:0] quotient_temp[WIDTHN:0];
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reg [WIDTHN-1:0] remain_temp[WIDTHN:0];
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reg [WIDTHN-1:0] denom_copy[WIDTHN:0];
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always @* begin
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rfd = 1'b0; //for PIPELINE enable, rfd is not used
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denom_copy[0] = denom_temp;
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remain_temp[0] = {WIDTHN{1'b0}};
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quotient_temp[0] = numer_temp;
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end
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for (i=0; i<WIDTHN; i=i+1) begin
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assign sub[i] = {remain_temp[i][(WIDTHN-2):0], quotient_temp[i][(WIDTHN-1)]} - denom_copy[i];
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if (i < LATENCY) begin
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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remain_temp[i+1] <= {WIDTHN{1'b0}};
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quotient_temp[i+1] <= {WIDTHN{1'b0}};
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denom_copy[i+1] <= {WIDTHN{1'b0}};
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end
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else if(clken) begin
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denom_copy[i+1] <= denom_copy[i];
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if (sub[i][(WIDTHN)] == 0) begin
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remain_temp[i+1] <= sub[i][(WIDTHN-1):0];
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quotient_temp[i+1] <= {quotient_temp[i][(WIDTHN-2):0], 1'b1};
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end
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else begin
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remain_temp[i+1] <= {remain_temp[i][(WIDTHN-2):0], quotient_temp[i][(WIDTHN-1)]};
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quotient_temp[i+1] <= {quotient_temp[i][(WIDTHN-2):0], 1'b0};
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end
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end
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end
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end
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else begin
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always @* begin
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denom_copy[i+1] = denom_copy[i];
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end
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always @* begin
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if (sub[i][(WIDTHN)] == 0) begin
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remain_temp[i+1] = sub[i][(WIDTHN-1):0];
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end
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else begin
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remain_temp[i+1] = {remain_temp[i][(WIDTHN-2):0], quotient_temp[i][(WIDTHN-1)]};
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end
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end
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always @* begin
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if (sub[i][(WIDTHN)] == 0) begin
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quotient_temp[i+1] = {quotient_temp[i][(WIDTHN-2):0], 1'b1};
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end
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else begin
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quotient_temp[i+1] = {quotient_temp[i][(WIDTHN-2):0], 1'b0};
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end
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end
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end
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end
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if (NREPRESENTATION == "SIGNED" || DREPRESENTATION == "SIGNED") begin
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assign quotient_copy = sign_quotient[LATENCY] ? (~quotient_temp[WIDTHN] + 1) : quotient_temp[WIDTHN];
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end
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else begin
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assign quotient_copy = quotient_temp[WIDTHN];
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end
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assign remain_copy = remain_temp[WIDTHN];
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end
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else begin : non_pipeline
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localparam COMBI_STAGE = WIDTHN - LATENCY;
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wire [(WIDTHN-1):0] denom_sub;
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reg [WIDTHN-1:0] denom_reg;
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reg [(WIDTHN-1):0] quotient_reg;
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reg [(WIDTHN-1):0] remain_reg;
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wire [(WIDTHN+1):0] sub;
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reg [(WIDTHN-1):0] quotient_combi[COMBI_STAGE:0];
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reg [WIDTHN-1:0] remain_combi[COMBI_STAGE:0];
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wire [(WIDTHN+1):0] sub_combi[COMBI_STAGE:0];
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reg clken_IP;
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assign denom_sub = {{(WIDTHN-WIDTHD){1'b0}},denom_temp};
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always @(posedge clk,posedge reset) begin
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if(reset) begin
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clken_IP <= 1'b0;
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end
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else begin
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clken_IP <= clken;
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end
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end
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if(LATENCY > 0) begin
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reg [LATENCY-1:0] ready;
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assign sub = (ready[0] || ~clken_IP) ? ({{(WIDTHN-2){1'b0}}, numer_temp[(WIDTHN-1)]} - denom_sub) : ({remain_reg[(WIDTHN-2):0], quotient_reg[(WIDTHN-1)]} - denom_reg);
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always @(posedge clk,posedge reset) begin
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if(reset) begin
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ready <= {LATENCY{1'b0}};
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end
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else if(clken) begin
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if(ready[0] || ~clken_IP) begin
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ready <= {1'b1, {LATENCY-1{1'b0}}};
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end
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else begin
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ready <= {1'b0, ready[LATENCY-1:1]};
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end
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end
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else begin
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ready <= {LATENCY{1'b0}};
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end
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end
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always @(posedge clk,posedge reset) begin
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if(reset) begin
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remain_reg <= {WIDTHN{1'b0}};
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quotient_reg <= {WIDTHN{1'b0}};
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denom_reg <= {WIDTHN{1'b0}};
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end
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else if(clken) begin
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if(ready[0] || ~clken_IP) begin
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denom_reg <= denom_temp;
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if (sub[(WIDTHN)] == 0) begin
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remain_reg <= sub[(WIDTHN-1):0];
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quotient_reg <= {numer_temp[(WIDTHN-2):0], 1'b1};
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end
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else begin
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remain_reg <= {{(WIDTHN-2){1'b0}}, numer_temp[(WIDTHN-1)]};
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quotient_reg <= {numer_temp[(WIDTHN-2):0], 1'b0};
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end
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end
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else begin
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if (sub[(WIDTHN)] == 0) begin
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remain_reg <= sub[(WIDTHN-1):0];
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quotient_reg <= {quotient_reg[(WIDTHN-2):0], 1'b1};
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end
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else begin
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remain_reg <= {remain_reg[(WIDTHN-2):0], quotient_reg[(WIDTHN-1)]};
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quotient_reg <= {quotient_reg[(WIDTHN-2):0], 1'b0};
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end
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end
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end
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end
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if (ENABLE_OUTREG) begin
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always @(posedge clk,posedge reset) begin
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if (reset) begin
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rfd <= 1'b0;
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end
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else begin
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rfd <= ready[0];
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end
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end
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end
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else begin
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always @* begin
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rfd = ready[0];
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end
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end
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always @* begin
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quotient_combi[0] = quotient_reg;
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remain_combi[0] = remain_reg;
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end
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for (i=0; i<COMBI_STAGE; i=i+1) begin
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assign sub_combi[i] = {remain_combi[i][(WIDTHN-2):0], quotient_combi[i][(WIDTHN-1)]} - denom_reg;
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end
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end
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else begin
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always @* begin
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rfd = 1'b1;
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end
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always @* begin
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quotient_combi[0] = numer_temp;
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remain_combi[0] = {WIDTHN{1'b0}};
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end
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for (i=0; i<COMBI_STAGE; i=i+1) begin
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assign sub_combi[i] = {remain_combi[i][(WIDTHN-2):0], quotient_combi[i][(WIDTHN-1)]} - denom_sub;
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end
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end
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for (i=0; i<COMBI_STAGE; i=i+1) begin
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always @* begin
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if(sub_combi[i][(WIDTHN)] == 0) begin
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remain_combi [i+1] = sub_combi[i][(WIDTHN-1):0];
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quotient_combi [i+1] = {quotient_combi[i][(WIDTHN-2):0], 1'b1};
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end
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else begin
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remain_combi[i+1] = {remain_combi[i][(WIDTHN-2):0], quotient_combi[i][(WIDTHN-1)]};
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quotient_combi[i+1] = {quotient_combi[i][(WIDTHN-2):0], 1'b0};
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end
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end
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end
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if(NREPRESENTATION == "SIGNED" || DREPRESENTATION == "SIGNED") begin
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assign quotient_copy = sign_quotient[LATENCY] ? (~quotient_combi[COMBI_STAGE] + 1): quotient_combi[COMBI_STAGE];//
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end
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else begin
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assign quotient_copy = quotient_combi[COMBI_STAGE];
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end
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assign remain_copy = remain_combi[COMBI_STAGE];
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end
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if (ENABLE_OUTREG) begin
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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quotient <= {WIDTHN{1'b0}};
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remain <= {WIDTHD{1'b0}};
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end
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else begin
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quotient <= quotient_copy;
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remain <= remain_copy;
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end
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end
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end
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else begin
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always @* begin
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quotient = quotient_copy;
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remain = remain_copy;
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end
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end
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end
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endgenerate
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endmodule
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`undef IP_UUID
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`undef IP_NAME_CONCAT
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`undef IP_MODULE_NAME
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