8181a3a583
The pipelining allows the cpu to run at a faster clock speed but results in latency. At the current 2 MHz, there is 1 cycle of latency which is negligible because the 6502 cannot do sequential data memory accesses. In the future, there will have to be some sort of status flag or interrupt showing that the divider is ready.
33 lines
999 B
JSON
33 lines
999 B
JSON
{
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"args": [
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"-o",
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"divider",
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"--base_path",
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"/home/byron/Projects/super6502/hw/efinix_fpga/ip",
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"--vlnv",
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{
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"vendor": "efinixinc.com",
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"library": "arithmetic",
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"name": "efx_divider",
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"version": "2.2"
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}
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],
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"conf": {
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"NREPRESENTATION": "0",
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"WIDTHN": "16",
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"WIDTHD": "16",
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"DREPRESENTATION": "0",
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"PIPELINE": "0",
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"LATENCY": "16"
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},
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"output": {
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"external_source_source": [
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"/home/byron/Projects/super6502/hw/efinix_fpga/ip/divider/divider.v",
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"/home/byron/Projects/super6502/hw/efinix_fpga/ip/divider/divider_define.vh",
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"/home/byron/Projects/super6502/hw/efinix_fpga/ip/divider/divider_tmpl.vhd",
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"/home/byron/Projects/super6502/hw/efinix_fpga/ip/divider/divider_tmpl.v"
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]
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},
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"sw_version": "2022.2.322",
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"generated_date": "2023-01-05T23:44:10.084005"
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} |