Files
super6502/hw/fpga/.gitlab-ci.yml
2022-03-05 19:11:53 -06:00

12 lines
162 B
YAML

default:
image: bslathi19/modelsim_18.1:lite
tags:
- docker
build1:
stage: build
script:
- cd hw/fpga/
- quartus_map super6502 -c super6502