Byron Lathi 8be97b45ae Move to 4 TCP units for synthesis ...

Otherwise it does not fit in the T20

2024-09-09 22:59:59 -07:00

..

constraints

Add basic project with cpu, ram and rom

2024-03-02 22:46:48 -08:00

ip/sdram_controller

Fix sdram sim

2024-03-03 21:33:28 -08:00

src

Move to 4 TCP units for synthesis

2024-09-09 22:59:59 -07:00

.gitignore

Add tcp regs and switch to verilator

2024-08-17 11:56:01 -07:00

addr_map.mem

integrate sd controller and super simple tb

2024-03-10 11:31:07 -07:00

Makefile

Add program target to makefiles

2024-03-10 22:25:29 -07:00

sources.list

Mega commit to kick things off

2024-09-01 22:23:21 -07:00

super6502_fpga.peri.xml

Reset renaming, set card_detect

2024-07-17 00:43:30 -07:00

super6502_fpga.xml

Move to 4 TCP units for synthesis

2024-09-09 22:59:59 -07:00