b8161e3082
The Logic analyzer isn't that useful anyway since it does not track rising and falling edges.
29 lines
403 B
Systemverilog
29 lines
403 B
Systemverilog
module leds
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(
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input clk,
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input [7:0] i_data,
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output logic [7:0] o_data,
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input cs,
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input rwb,
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output logic [7:0] o_leds
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);
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logic re, we;
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assign re = rwb & cs;
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assign we = ~rwb & cs;
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logic [7:0] _data;
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assign o_leds = ~_data;
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always @(negedge clk) begin
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if (re) begin
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o_data <= _data;
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end
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else if (we) begin
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_data <= i_data;
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end
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end
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endmodule |