24 lines
703 B
Systemverilog
24 lines
703 B
Systemverilog
module addr_decode
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(
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input [15:0] i_addr,
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output o_rom_cs,
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output o_leds_cs,
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output o_timer_cs,
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output o_multiplier_cs,
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output o_divider_cs,
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output o_uart_cs,
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output o_sdcard_cs,
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output o_sdram_cs
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);
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assign o_rom_cs = i_addr >= 16'hf000 && i_addr <= 16'hffff;
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assign o_timer_cs = i_addr >= 16'heff8 && i_addr <= 16'heffb;
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assign o_multiplier_cs = i_addr >= 16'heff0 && i_addr <= 16'heff7;
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assign o_divider_cs = i_addr >= 16'hefe8 && i_addr <= 16'hefef;
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assign o_uart_cs = i_addr >= 16'hefe6 && i_addr <= 16'hefe7;
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assign o_sdcard_cs = i_addr >= 16'hefd8 && i_addr <= 16'hefdf;
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assign o_leds_cs = i_addr == 16'hefff;
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assign o_sdram_cs = i_addr < 16'h8000;
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endmodule |