Byron Lathi 9b2a40df06 Add tcp regs and switch to verilator

2024-08-17 11:56:01 -07:00

..

constraints

Add basic project with cpu, ram and rom

2024-03-02 22:46:48 -08:00

ip/sdram_controller

Fix sdram sim

2024-03-03 21:33:28 -08:00

src

Add tcp regs and switch to verilator

2024-08-17 11:56:01 -07:00

.gitignore

Add tcp regs and switch to verilator

2024-08-17 11:56:01 -07:00

addr_map.mem

integrate sd controller and super simple tb

2024-03-10 11:31:07 -07:00

Makefile

Add program target to makefiles

2024-03-10 22:25:29 -07:00

sources.list

Add tcp regs and switch to verilator

2024-08-17 11:56:01 -07:00

super6502_fpga.peri.xml

Reset renaming, set card_detect

2024-07-17 00:43:30 -07:00

super6502_fpga.xml

Fix sdspi, add missing source file

2024-07-31 22:02:47 -07:00