627b6a746a
This also increases the number of registers to 4, one more for the high pair of displays, and a final one for a mask register which has not been implemented yet.
13 lines
263 B
Systemverilog
13 lines
263 B
Systemverilog
module addr_decode(
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input logic [15:0] addr,
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output logic ram_cs,
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output logic rom_cs,
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output logic hex_cs
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);
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assign rom_cs = addr[15];
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assign ram_cs = ~addr[15] && addr < 16'h7ff0;
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assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff4;
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endmodule
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