96 lines
1.8 KiB
YAML
96 lines
1.8 KiB
YAML
default:
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tags:
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- docker
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variables:
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GIT_SUBMODULE_STRATEGY: recursive
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stages:
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- build_toolchain
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- build_sw
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- build_hw
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- test
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build-cc65:
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stage: build_toolchain
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image: gcc
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script:
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- cd sw
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- make toolchain
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artifacts:
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paths:
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- sw/cc65/bin
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- sw/cc65/lib
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build-kernel:
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stage: build_sw
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image: gcc
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script:
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- cd sw/kernel
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- make
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build-bootloader:
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stage: build_sw
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image: gcc
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script:
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- cd sw/bootloader
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- make
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artifacts:
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paths:
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- sw/bootloader/bootloader.hex
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expire_in: 1 week
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build-fpga:
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stage: build_hw
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dependencies:
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- build-bootloader
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image: bslathi19/modelsim_18.1:lite
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script:
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- cd hw/fpga/
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- qsys-generate /builds/bslathi19/super6502/hw/fpga/sdram_platform.qsys --synthesis=VERILOG --output-directory=/builds/bslathi19/super6502/hw/fpga/sdram_platform --family="MAX 10" --part=10M50DAF484C7G
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- quartus_map super6502 -c super6502
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test_addr_decode:
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stage: test
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image: bslathi19/modelsim_18.1:lite
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script:
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- cd hw/fpga/simulation/modelsim/
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- vsim -do "do cs_testbench.do"
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test_bb_spi:
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stage: test
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image: bslathi19/modelsim_18.1:lite
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script:
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- cd hw/fpga/simulation/modelsim/
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- vsim -do "do bb_spi_testbench.do"
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test-sw:
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stage: test
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image: gcc
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script:
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- cd sw/kernel
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- make test
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test_mm:
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stage: test
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image: bslathi19/modelsim_18.1:lite
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script:
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- cd hw/fpga/simulation/modelsim/
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- vsim -do "do mm_testbench.do"
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test_crc7:
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stage: test
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image: bslathi19/modelsim_18.1:lite
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script:
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- cd hw/fpga/simulation/modelsim/
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- vsim -do "do crc7_testbench.do"
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test_sd_cmd:
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stage: test
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image: bslathi19/modelsim_18.1:lite
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script:
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- cd hw/fpga/simulation/modelsim/
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- vsim -do "sd_cmd_testbench.do"
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