47 lines
1.3 KiB
Makefile
47 lines
1.3 KiB
Makefile
FPGA_SRCS_LIST=../../sources.list
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SIM_SRCS_LIST=sources.list
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BAD_SOURCES_LIST=stubs.list
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SUPER6502_FPGA_SOURCES=$(shell rtl-manifest $(FPGA_SRCS_LIST))
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BAD_SOURCES=$(shell rtl-manifest $(BAD_SOURCES_LIST))
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GOOD_FPGA_SOURCES=$(filter-out $(BAD_SOURCES), $(SUPER6502_FPGA_SOURCES))
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SIM_SOURCES=$(shell cat $(SIM_SRCS_LIST))
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INCLUDE=include/sdram_controller_define.vh
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TB_NAME=sim_top
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COPY_FILES=addr_map.mem init_hex.mem
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SD_IMAGE=sd_image.bin
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FLAGS=-DSIM -DRTL_SIM -DVERILATOR -DSDIO_AXI
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# IVERILOG=$(REPO_TOP)/../iverilog/local/bin/iverilog -v
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IVERILOG=iverilog
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all: waves
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waves: $(TB_NAME)
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# ./$(TB_NAME) -fst
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./obj_dir/Vsim_top
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$(TB_NAME): $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) $(COPY_FILES) $(SD_IMAGE)
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# $(IVERILOG) -g2005-sv $(FLAGS) -s $@ -o $@ $(INCLUDE) $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) -I ../../
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verilator --binary $(FLAGS) $(INCLUDE) $(GOOD_FPGA_SOURCES) $(SIM_SOURCES) +incdir+../../ -Wno-BLKANDNBLK -Wno-fatal -j 16 --top sim_top --trace-fst -Wno-ASSIGNDLY
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$(SD_IMAGE):
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dd if=/dev/urandom bs=1 count=65536 of=$(SD_IMAGE)
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# I feel like this should also realize that the outside files are newer...
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.PHONY: $(COPY_FILES)
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$(COPY_FILES): ../../$@
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cp ../../$@ .
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.PHONY: clean
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clean:
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rm -rf $(COPY_FILES)
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rm -rf $(TB_NAME)
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rm -rf sim_top.vcd
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rm -rf obj_dir
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