a836643807
Now that the ROM is just a bootloader and the kernel is stored on the SD card, we do not need to be constantly changing the ROM. Disabling the memory editor dramatically reduces compilation time which will be useful when implementing FPGA features in the future.
165 lines
6.4 KiB
Verilog
165 lines
6.4 KiB
Verilog
// megafunction wizard: %ROM: 1-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram
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// ============================================================
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// File Name: rom.v
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// Megafunction Name(s):
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// altsyncram
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
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// ************************************************************
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//Copyright (C) 2018 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module rom (
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address,
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clock,
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q);
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input [14:0] address;
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input clock;
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output [7:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [7:0] sub_wire0;
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wire [7:0] q = sub_wire0[7:0];
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altsyncram altsyncram_component (
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.address_a (address),
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.clock0 (clock),
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.q_a (sub_wire0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.address_b (1'b1),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_a ({8{1'b1}}),
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.data_b (1'b1),
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.eccstatus (),
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.q_b (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_a (1'b0),
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.wren_b (1'b0));
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defparam
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altsyncram_component.address_aclr_a = "NONE",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_output_a = "BYPASS",
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`ifdef NO_PLI
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altsyncram_component.init_file = "../../sw/bootloader/bootloader.rif"
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`else
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altsyncram_component.init_file = "../../sw/bootloader/bootloader.hex"
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`endif
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,
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altsyncram_component.intended_device_family = "MAX 10",
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altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 32768,
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altsyncram_component.operation_mode = "ROM",
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altsyncram_component.outdata_aclr_a = "NONE",
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altsyncram_component.outdata_reg_a = "UNREGISTERED",
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altsyncram_component.widthad_a = 15,
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altsyncram_component.width_a = 8,
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altsyncram_component.width_byteena_a = 1;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
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// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
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// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: Clken NUMERIC "0"
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// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "ROM0"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING "../../sw/bootloader/bootloader.hex"
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// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
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// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
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// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
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// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
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// Retrieval info: PRIVATE: WidthData NUMERIC "8"
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// Retrieval info: PRIVATE: rden NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: INIT_FILE STRING "../../sw/bootloader/bootloader.hex"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
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// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
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// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
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// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
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// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
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// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL rom.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rom.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rom.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rom.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rom_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rom_bb.v FALSE
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// Retrieval info: LIB_FILE: altera_mf
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