97 lines
2.2 KiB
Systemverilog
97 lines
2.2 KiB
Systemverilog
module spi_controller(
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input i_clk,
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input i_rst,
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input i_cs,
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input i_rwb,
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input [1:0] i_addr,
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input [7:0] i_data,
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output logic [7:0] o_data,
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output o_spi_cs,
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output o_spi_clk,
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output o_spi_mosi,
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input i_spi_miso
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);
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// We need a speed register
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// an input data register
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// and an output data register
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// and then a control register for cs
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logic [7:0] r_baud_rate;
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logic [7:0] r_input_data;
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logic [7:0] r_output_data;
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logic [7:0] r_control;
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logic [8:0] r_clock_counter;
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logic active;
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logic [2:0] count;
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logic spi_clk;
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logic r_spi_mosi;
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assign o_spi_cs = ~r_control[0];
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assign o_spi_clk = spi_clk;
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assign o_spi_mosi = r_spi_mosi;
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always @(negedge i_clk) begin
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if (i_rst) begin
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r_baud_rate <= 8'h1;
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r_input_data <= '0;
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r_output_data <= '0;
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r_control <= '0;
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r_clock_counter <= '0;
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count <= '0;
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spi_clk <= '0;
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active <= '0;
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end else begin
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if (~i_rwb & i_cs) begin
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unique case (i_addr)
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0: r_baud_rate <= i_data;
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1:;
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2: begin
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r_output_data <= i_data;
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active <= '1;
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end
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3: r_control <= i_data;
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endcase
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end
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if (active) begin
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r_spi_mosi <= r_output_data[7];
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r_clock_counter <= r_clock_counter + 9'b1;
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if (r_clock_counter >= r_baud_rate) begin
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r_clock_counter <= '0;
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spi_clk <= ~spi_clk;
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// rising edge
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if (spi_clk == '0) begin
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r_output_data <= r_output_data << 1;
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count <= count + 1;
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end
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// falling edge
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if (spi_clk == '1) begin
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r_input_data <= {r_input_data[6:0], i_spi_miso};
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if (count == '0) begin
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active <= '0;
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end
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end
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end
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end
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end
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end
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always_comb begin
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unique case (i_addr)
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0: o_data = r_baud_rate;
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1: o_data = r_input_data;
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2:;
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3: o_data = {active, r_control[6:0]};
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endcase
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end
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endmodule |