75 lines
1.3 KiB
Systemverilog
75 lines
1.3 KiB
Systemverilog
module testbench();
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timeunit 10ns;
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timeprecision 1ns;
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logic clk, rst, spi_cs;
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logic [7:0] data_in, data_out;
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logic rw;
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logic SPI_SSn, SPI_MOSI, SPI_SCLK, SPI_MISO;
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logic SPI_slave_IRQ;
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bb_spi_controller dut(.*);
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always #5 clk = clk === 1'b0;
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task write_byte(input logic [8:0] wdata);
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for (int i = 0; i < 8; i++) begin
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write_bit(8'b0 + (wdata[i] << 2));
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write_bit(8'b1 + (wdata[i] << 2));
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end
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write_bit(8'b0);
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endtask
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task write_bit(input logic [8:0] wdata);
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@(negedge clk);
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spi_cs <= '1;
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data_in <= wdata;
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rw <= '0;
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@(posedge clk);
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endtask
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task read(output logic [8:0] rdata);
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@(negedge clk);
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spi_cs <= '1;
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rdata <= data_out;
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rw <= '1;
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@(posedge clk);
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endtask
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always @(posedge SPI_SCLK) begin
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assert(SPI_MOSI == data_in[2]) else begin
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$error("SPI_MOSI data error");
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end
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end
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initial begin : TEST_VECTORS
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SPI_slave_IRQ <= '0;
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SPI_MISO <= '0;
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rst <= '1;
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repeat(5) @(posedge clk);
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rst <= '0;
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@(posedge clk);
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write_byte(8'ha5);
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repeat(5) @(posedge clk);
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SPI_slave_IRQ <= '1;
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@(posedge clk);
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@(posedge clk);
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assert (data_out[4] == '1) else begin
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$error("IRQ expected");
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end
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repeat(5) @(posedge clk);
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$finish();
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end
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endmodule
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