Files
super6502/hw/fpga/simulation/modelsim/bb_spi_testbench.do
Byron Lathi ad55f986f5 Add bb_spi_controller
Bit banged spi controller, very simple but very slow.
2022-03-08 15:26:01 -06:00

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if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
vlog -sv -work work {../../bb_spi_controller.sv}
vlog -sv -work work {../../hvl/bb_spi_testbench.sv}
vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixv_ver -L stratixv_hssi_ver -L stratixv_pcie_hip_ver -L rtl_work -L work -voptargs="+acc" testbench
add wave -group {dut} -radix hexadecimal sim:/testbench/dut/*
onfinish stop
run -all
if { [coverage attribute -name TESTSTATUS -concise] == "1"} {
echo Warning
quit -f -code 0
}
quit -code [coverage attribute -name TESTSTATUS -concise]