100 lines
4.9 KiB
Plaintext
100 lines
4.9 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2018 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
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# Date created = 16:36:56 March 05, 2022
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# super6502_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "MAX 10"
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set_global_assignment -name DEVICE 10M50DAF484C7G
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set_global_assignment -name TOP_LEVEL_ENTITY super6502
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:36:56 MARCH 05, 2022"
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set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
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set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_location_assignment PIN_V10 -to cpu_led
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set_location_assignment PIN_W10 -to cpu_vpb
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set_location_assignment PIN_V9 -to cpu_resb
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set_location_assignment PIN_W9 -to cpu_rdy
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set_location_assignment PIN_V8 -to cpu_sob
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set_location_assignment PIN_V7 -to cpu_phi2
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set_location_assignment PIN_W6 -to cpu_be
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set_location_assignment PIN_W5 -to cpu_rwb
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set_location_assignment PIN_AA14 -to cpu_data[0]
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set_location_assignment PIN_W12 -to cpu_data[1]
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set_location_assignment PIN_AB12 -to cpu_data[2]
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set_location_assignment PIN_AB11 -to cpu_data[3]
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set_location_assignment PIN_AB10 -to cpu_data[4]
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set_location_assignment PIN_AA9 -to cpu_data[5]
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set_location_assignment PIN_AA8 -to cpu_data[6]
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set_location_assignment PIN_AA7 -to cpu_data[7]
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set_location_assignment PIN_AA6 -to cpu_addr[15]
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set_location_assignment PIN_AA5 -to cpu_addr[14]
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set_location_assignment PIN_AB3 -to cpu_addr[13]
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set_location_assignment PIN_AB2 -to cpu_addr[12]
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set_location_assignment PIN_AA2 -to cpu_addr[11]
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set_location_assignment PIN_Y3 -to cpu_addr[10]
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set_location_assignment PIN_Y4 -to cpu_addr[9]
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set_location_assignment PIN_Y5 -to cpu_addr[8]
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set_location_assignment PIN_Y6 -to cpu_addr[7]
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set_location_assignment PIN_Y7 -to cpu_addr[6]
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set_location_assignment PIN_Y8 -to cpu_addr[5]
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set_location_assignment PIN_AA10 -to cpu_addr[4]
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set_location_assignment PIN_W11 -to cpu_addr[3]
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set_location_assignment PIN_Y11 -to cpu_addr[2]
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set_location_assignment PIN_AB13 -to cpu_addr[1]
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set_location_assignment PIN_W13 -to cpu_addr[0]
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set_location_assignment PIN_AA15 -to cpu_sync
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set_location_assignment PIN_V5 -to cpu_nmib
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set_location_assignment PIN_W7 -to cpu_mlb
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set_location_assignment PIN_W8 -to cpu_irqb
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set_location_assignment PIN_P11 -to clk
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set_location_assignment PIN_B8 -to rst
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name SYSTEMVERILOG_FILE bb_spi_controller.sv
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set_global_assignment -name SYSTEMVERILOG_FILE super6502.sv
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set_global_assignment -name QIP_FILE ram.qip
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set_global_assignment -name SDC_FILE super6502.sdc
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set_global_assignment -name QIP_FILE rom.qip
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" |