3e69109474
These are just some values that I found from an example program. This does not test every possible value.
66 lines
1.5 KiB
Systemverilog
66 lines
1.5 KiB
Systemverilog
module testbench();
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timeunit 10ns;
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timeprecision 1ns;
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logic clk;
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logic rst;
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logic load;
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logic [39:0] data_in;
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logic [6:0] crc_out;
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logic valid;
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crc7 dut(.*);
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always #1 clk = clk === 1'b0;
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task create_sd_packet(logic [5:0] cmd, logic [31:0] data, output logic [47:0] _packet);
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@(posedge clk);
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data_in <= {1'b0, 1'b1, cmd, data};
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load <= '1;
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@(posedge clk);
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load <= '0;
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while (~valid) begin
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//$display("Working %b", dut.data);
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@(posedge clk);
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end
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_packet = {1'b0, 1'b1, cmd, data, crc_out, 1'b1};
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endtask
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logic [47:0] packet;
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initial begin
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rst <= '1;
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repeat(5) @(posedge clk);
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rst <= '0;
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create_sd_packet(6'h0, 32'h0, packet);
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$display("Result: %x", packet);
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assert(packet == 48'h400000000095) else
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$error("Bad crc7. Got %x expected %x", packet, 48'h400000000095);
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create_sd_packet(6'd8, 32'h1aa, packet);
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$display("Result: %x", packet);
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assert(packet == 48'h48000001aa87) else
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$error("Bad crc7. Got %x expected %x", packet, 48'h48000001aa87);
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create_sd_packet(6'd55, 32'h0, packet);
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$display("Result: %x", packet);
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assert(packet == 48'h770000000065) else
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$error("Bad crc7. Got %x expected %x", packet, 48'h770000000065);
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create_sd_packet(6'd41, 32'h40180000, packet);
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$display("Result: %x", packet);
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assert(packet == 48'h694018000019) else
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$error("Bad crc7. Got %x expected %x", packet, 48'h694018000019);
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$finish();
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end
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endmodule
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