50b0860137
Updates the testbench to simulate writes with more correct timings. Writes take two clock cycles since the cpu runs at half speed.
89 lines
1.7 KiB
Systemverilog
89 lines
1.7 KiB
Systemverilog
module testbench();
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timeunit 10ns;
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timeprecision 1ns;
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logic clk;
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logic rw;
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logic clk_50;
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logic rst;
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logic [2:0] addr;
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logic [7:0] data;
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logic cs;
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logic i_sd_cmd;
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logic o_sd_cmd;
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logic i_sd_data;
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logic o_sd_data;
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logic cpu_phi2;
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always @(posedge clk) begin
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cpu_phi2 <= cpu_phi2 === '0;
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end
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sd_controller dut(
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.sd_clk(cpu_phi2),
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.*);
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always #1 clk_50 = clk_50 === 1'b0;
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always #100 clk = clk === 1'b0;
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task write_reg(logic [3:0] _addr, logic [7:0] _data);
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@(posedge clk);
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cs = '1;
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addr = _addr;
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rw = '0;
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data = '1;
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@(posedge clk);
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data = _data;
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@(posedge clk);
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cs = '0;
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rw = '1;
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endtask
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task verify_cmd(logic [5:0] cmd, logic [31:0] arg, logic [47:0] verify);
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write_reg(0, arg[7:0]);
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write_reg(1, arg[15:8]);
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write_reg(2, arg[23:16]);
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write_reg(3, arg[31:24]);
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write_reg(4, cmd);
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$display("arg: %x", dut.arg);
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$display("dut.cmd: %x", dut.cmd);
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@(posedge clk);
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@(posedge clk);
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while (dut.state.macro == dut.TXCMD) begin
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assert(o_sd_cmd == verify[47-dut.state.count]) else begin
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$error("cmd output error: Expected %h:%b, got %h:%b",
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47-dut.state.count, verify[47-dut.state.count],
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47-dut.state.count, o_sd_cmd);
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end
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@(negedge clk);
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end
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endtask
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localparam cmd0 = 48'h400000000095;
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localparam cmd8 = 48'h48000001aa87;
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localparam cmd55 = 48'h770000000065;
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localparam cmd41 = 48'h694018000019;
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initial begin
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rst <= '1;
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repeat(5) @(posedge clk);
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rst <= '0;
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verify_cmd(0, 0, cmd0);
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verify_cmd(8, 'h1aa, cmd8);
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verify_cmd('d55, 0, cmd55);
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verify_cmd('d41, 'h40180000, cmd41);
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$finish();
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end
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endmodule |