70 lines
2.7 KiB
Markdown
70 lines
2.7 KiB
Markdown
# Super6502
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## Overview
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Super6502 is a microcomputer system powered by a 65C02 CPU. The goal of this
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project is to create a computer system with modern features and the ability to
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run modern software on an unmodified 65C02 core. While the project is almost
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entirely contained in an FPGA, this rule is enforced by using an off the shelf
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CPU.
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## Goals
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There are a few goals that I have for this project.
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The number 1 goal is to create a pre-emptive multitasking operating system with
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virtual memory.
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1. Connect it to the internet
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2. Boot linux (lol)
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Along the way, there are a few milestones that I want to reach:
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* USB support, including mass storage and peripherals
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* HDMI Display output
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* Ethernet
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## Details
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Currently, the project is built around an Efinix Trion T20F256 Development board.
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I also have a breakout board with an SD card slot, a MAX3421E, and an audio codec
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(that I forget the pn) which I got at school. Right now I only use the SD card.
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The development board is sparse, but it includes SDRAM and enough headers to add
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any other peripherals.
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I designed a board to plug into one of the headers which exposes nearly all the pins
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of a 65C02 directly to the FPGA, with no external circuitry except for 2 pull-up
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resistors.
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The heart of the project is `super6502.sv`. This file contains all of the various
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parts of the project. It contains a small boot rom, but the rest of the code is
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loaded from an SD card. All of the peripherals are also instantiated here, and there
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is a block at the top for address decoding. It currently contains a very simple MMU
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which allows the CPU access to the full 32MB address space. Other peripherals include
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a timer, leds, hardware multiplier and divider, a uart, an spi controller (for the sd
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card), an interrupt controller, and the SDRAM controller.
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The SDRAM controller is the one supplied by the FPGA manufacturer, efinix, but contained
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in a wrapper which adapts the native bus to the 6502 bus.
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One aspect of the project that I want to improve on is bus interoperability. There is
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a huge world of IP that is available if I support AXI or WishBone, but at the moment
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I do not.
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## Simulation Effort
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Because I mostly work on this project while on the bus going to/from work, I can't be
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iteratively testing on the hardware. I was inspired by the simulation setup we have at
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work for the Starlink ASICs and decided to try and implement something similar, albeit
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with only free tools at my disposal. It mostly works, but is very slow. Booting the
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kernel takes nearly an hour(!), and that is with no kernel features or functionality.
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For this reason, the IP blocks have standalone simulations as well as full system
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simulations
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## Contributing
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While I appreciate feedback, this my own personal project and I will not accept
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external contributions. |