171 lines
3.3 KiB
Systemverilog
171 lines
3.3 KiB
Systemverilog
`timescale 1ns/1ps
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module interrupt_controller_tb();
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logic r_clk_cpu;
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// clk_cpu
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initial begin
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r_clk_cpu <= '1;
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forever begin
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#125 r_clk_cpu <= ~r_clk_cpu;
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end
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end
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logic reset;
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logic addr;
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logic [7:0] i_data;
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logic [7:0] o_data;
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logic cs;
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logic rwb;
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logic [255:0] int_in;
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logic int_out;
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interrupt_controller u_interrupt_controller(
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.clk(r_clk_cpu),
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.reset(reset),
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.i_data(i_data),
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.o_data(o_data),
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.addr(addr),
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.cs(cs),
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.rwb(rwb),
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.int_in(int_in),
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.int_out(int_out)
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);
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/* Test Level triggered IRQ by triggering IRQ0
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* and then clearing it,
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*/
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task test_edge_irq();
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$display("Testing Edge IRQ");
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do_reset();
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set_enable(255'hff);
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set_edge_type(255'h0);
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set_interrupts(1);
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assert (int_out == 1) else begin
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errors = errors + 1;
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$error("Interrupt should be high!");
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end
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send_eoi();
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assert (int_out == 0) else begin
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errors = errors + 1;
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$error("Interrupt should be low!");
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end
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set_interrupts(0);
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assert (int_out == 0) else begin
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errors = errors + 1;
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$error("Interrupt should be low!");
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end
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endtask
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task test_level_irq();
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$display("Testing level IRQ");
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do_reset();
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set_enable(255'hff);
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set_edge_type(255'hff);
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set_interrupts(1);
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assert (int_out == 1) else begin
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errors = errors + 1;
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$error("Interrupt should be high!");
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end
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send_eoi();
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assert (int_out == 1) else begin
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errors = errors + 1;
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$error("Interrupt should be high!");
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end
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set_interrupts(0);
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send_eoi();
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assert (int_out == 0) else begin
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errors = errors + 1;
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$error("Interrupt should be low!");
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end
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endtask
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int errors;
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initial begin
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errors = 0;
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test_edge_irq();
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test_level_irq();
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if (errors > 0)
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$finish_and_return(-1);
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else
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$finish();
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end
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initial
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begin
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$dumpfile("interrupt_controller_tb.vcd");
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$dumpvars(0,interrupt_controller_tb);
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end
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/* These should be shared */
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task write_reg(input logic [4:0] _addr, input logic [7:0] _data);
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@(negedge r_clk_cpu);
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cs <= '1;
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addr <= _addr;
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rwb <= '0;
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i_data <= '1;
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@(posedge r_clk_cpu);
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i_data <= _data;
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@(negedge r_clk_cpu);
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cs <= '0;
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rwb <= '1;
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@(posedge r_clk_cpu);
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endtask
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task read_reg(input logic [2:0] _addr, output logic [7:0] _data);
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@(negedge r_clk_cpu);
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cs <= '1;
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addr <= _addr;
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rwb <= '1;
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i_data <= '1;
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@(posedge r_clk_cpu);
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_data <= o_data;
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@(negedge r_clk_cpu);
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cs <= '0;
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rwb <= '1;
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@(posedge r_clk_cpu);
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endtask
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task do_reset();
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repeat (5) @(posedge r_clk_cpu);
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reset = 1;
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cs = 0;
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rwb = 1;
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addr = '0;
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i_data = '0;
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int_in = '0;
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repeat (5) @(posedge r_clk_cpu);
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reset = 0;
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repeat (5) @(posedge r_clk_cpu);
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endtask
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task set_enable(input logic [255:0] en);
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for (int i = 0; i < 16; i++) begin
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write_reg(0, 8'h10 | i);
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write_reg(1, en[8*i +: 8]);
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end
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endtask
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task set_edge_type(input logic [255:0] edge_type);
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for (int i = 0; i < 16; i++) begin
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write_reg(0, 8'h20 | i);
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write_reg(1, edge_type[8*i +: 8]);
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end
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endtask
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task set_interrupts(logic [255:0] ints);
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int_in = ints;
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@(posedge r_clk_cpu);
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endtask
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task send_eoi();
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write_reg(0, 8'hff);
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write_reg(1, 8'h01);
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endtask
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endmodule
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